Stacked PFET off-chip driver with a latch bias generator for ove

Details Stacked PFET off-chip driver with a latch bias generator for ove Stacked PFET off-chip driver with a latch bias generator for ove

1998-04-20

2000-10-31

Sherry, Michael J.

Electricity: electrical systems and devices

Safety and protection of systems and devices

Transient responsive

361 90, H02H 322

Patent

active

061412007

ABSTRACT:
Series-connected stacked PFETS are employed in an off-chip driver output stage. When the output driver is enabled, the gate of the PFET transistor directly connected to the output is biased by a latch at a voltage level of either one threshold voltage above ground or one threshold voltage below the power supply, depending on the data signal. This provides overvoltage protection even for overshoots and undershoots of one threshold voltage or less, and provides overvoltage protection below the threshold voltages required to activate conventional overvoltage protection devices. Tight tolerances for maximum gate voltages may thus be achieved, and smaller devices having thinner gate oxides utilized in the off-chip drivers of a processor or other device.

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