Stacked packages with interconnecting pins

Details Stacked packages with interconnecting pins Stacked packages with interconnecting pins

2008-05-27

2008-05-27

Clark, Jasmine J (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S723000, C257S777000, C257SE25006, C257SE25013, C257SE25018, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

07378726

ABSTRACT:
A system may include a first integrated circuit package including a first integrated circuit die and a first integrated circuit package substrate defining a first plurality of openings, a second integrated circuit package including a second integrated circuit die and a second integrated circuit package substrate defining a second plurality of openings, and a third substrate comprising a plurality of conductive projections. Each of the plurality of conductive projections may be disposed within a respective one of the first plurality of openings and a respective one of the second plurality of openings.

REFERENCES:
patent: 5241454 (1993-08-01), Ameen et al.
patent: 6476476 (2002-11-01), Glenn

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