Stacked-NMOS-triggered SCR device for ESD-protection

Details Stacked-NMOS-triggered SCR device for ESD-protection Stacked-NMOS-triggered SCR device for ESD-protection

2005-03-15

2005-03-15

Jackson, Stephen W. (Department: 2836)

Electricity: electrical systems and devices

Safety and protection of systems and devices

Load shunting by fault responsive means

C361S058000, C361S111000, C361S113000

Reexamination Certificate

active

06867957

ABSTRACT:
Transistors with very thin gate oxides are protected against oxide failure by cascading two or more transistors in series between an output pad and ground. The intermediate source/drain node between the two cascaded transistors is usually floating during an ESD test, delaying snapback turn-on of a parasitic lateral NPN transistor. This intermediate node is used to drive the gate of an upper trigger transistor. A lower trigger transistor has a gate node that is charged by the ESD pulse on the pad through a coupling capacitor. When the coupled ESD pulse turns on the trigger transistors, the trigger transistors turn on a silicon-controlled rectifier (SCR) that is integrated with the trigger transistors.

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