1982-11-19
1984-10-09
Edlow, Martin H.
357 44, 357 42, 357 59, H01L 2978, H01L 2702, H01L 2904
Patent
active
044764758
ABSTRACT:
In a stacked metal-oxide-semiconductor (SMOS) transistor, the transistor source, drain and channel each have a lower part formed in a silicon substrate and an upper part composed of recrystallized polysilicon. The device gate is located between the upper and lower channel parts. By vertically integrating a MOS transistor, performance limitations imposed by the direct scaling approach to device miniaturization are avoided.
REFERENCES:
patent: 4272880 (1981-06-01), Pashley
patent: 4309224 (1982-01-01), Shibata
Colinge et al. Conf. IEDM Wash D.C. USA Dec. 7-9, 1981, "ST-CMOS . . . Technology" pp. 557-560.
Boothroyd Albert R.
Calder Iain D.
Naem Abdalla A.
Naguib Hussein M.
Edlow Martin H.
Jackson Jerome
Northern Telecom Limited
Wilkinson Stuart L.
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