Stacked layered type semiconductor memory device

Details Stacked layered type semiconductor memory device Stacked layered type semiconductor memory device

2006-08-29

2006-08-29

Hoang, Huan (Department: 2827)

Static information storage and retrieval

Format or disposition of elements

C365S052000, C365S063000, C365S145000, C257S759000

Reexamination Certificate

active

07099173

ABSTRACT:
To provide laminated type semiconductor memory devices that can improve the yield of chips without complicating wirings and components. There are provided a plurality of laminated semiconductor chip layers, and chip selection pads provided on each of the chip layers, which are mutually connected across the chip layers, respectively, such that a chip selection signal for selecting each of the chip layers is commonly inputted in each of the chip layers. Each of the chip layers is equipped with program circuits each of which is capable of programming an output signal, and a chip selection judging circuit that judges a chip selection based on the chip selection signal and an output signal of the program circuit. The program circuit is equipped with writable nonvolatile memory cells, and a logical circuit that is connected to the nonvolatile memory cells and outputs a signal that is different depending on a recoded content in the nonvolatile memory cells, such that a step of melting fuses is not necessary.

REFERENCES:
patent: 5561622 (1996-10-01), Bertin et al.
patent: 6355976 (2002-03-01), Faris
patent: 6894392 (2005-05-01), Gudesen et al.
patent: 2004/0257847 (2004-12-01), Matsui et al.
patent: A 05-063138 (1993-03-01), None

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