Stacked-layer structure polysilicon emitter contacted p-n juncti

Details Stacked-layer structure polysilicon emitter contacted p-n juncti Stacked-layer structure polysilicon emitter contacted p-n juncti

1992-09-02

1994-09-13

Hille, Rolf

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257750, 257754, H01L 2348, H01L 2946

Patent

active

053471610

ABSTRACT:
A process is used to fabricate diodes having an emitter contacted p-n junction. A stack of n.sup.+ -type polysilicon layers are formed one upon the other upon a p-type silicon substrate. In an accordingly fabricated diode, native oxide layers that forms between the n.sup.+ -type polysilicon layer and the p-type substrate would be liable to be broken up, and thicker epitaxial layer would be formed between the same. The p-n junction is with a thickness of 0.05-0.2 .mu.m. As the diode is reverse-biased, for example at -5V, leakage current could be less than 1 n.ANG./cm.sup.2. The reverse-bias breakdown voltage could be larger than -100 V. When forward-biased, the ideality factor of the diode is close to unity.

REFERENCES:
patent: 4752813 (1988-06-01), Bhatia et al.
patent: 4994873 (1991-02-01), Madan
patent: 5057899 (1991-10-01), Samata et al.
patent: 5109256 (1992-04-01), De Long

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