Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2000-01-20
2002-09-17
Talbott, David L. (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S698000, C257S700000, C257S724000, C257S758000, C257S774000, C361S306300, C361S307000, C361S308100, C361S321200
Reexamination Certificate
active
06452250
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a semiconductor device, and more particularly to an integrated circuit structure and more particularly to a stacked combination of a semiconductor die and a flat capacitor.
BACKGROUND OF THE INVENTION
A logic circuit formed on a semiconductor die can be disrupted, or the circuit can even be permanently damaged, by electrostatic charge transients on connections to the circuit. The charge transients typically develop on the printed circuit board traces because such traces tend to function as antennas and pick up electromagnetic energy. The charge transient causes voltage spikes across capacitive junctions in the logic circuit in accordance with the formula
Voltage Spike=Charge Transient/Capacitance
The occurrence of such voltage spikes is independent of the fabrication technology and can disrupt or damage devices, such as field effect transistors (FETs) formed in bulk silicon wells, silicon on insulator SOI FETs formed on an SOI wafer, and other circuit elements fabricated utilizing known technologies.
While it is known that capacitors may be placed in close proximity to logic circuits on a printed circuit board to provide protection from charge transients as well as provide bypassing of high frequency noise, known capacitor structures occupy a significant amount of printed circuit board space. Furthermore, large capacitance capacitors are larger than small capacitance capacitors.
Accordingly, there is a strong need in the art for an integrated circuit structure that provides for a capacitor with a large capacitance to be located in close proximity to a semiconductor die without occupying significant area on a printed circuit board. Additionally, there is a strong need in the art for a electrostatic charge transient suppression structure which can provide enhanced protection from interruption and damage caused by charge transients in both conventional bulk silicon semiconductor circuits and in silicon on insulator semiconductor circuits.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide an integrated circuit which includes: a) a logic circuit implemented on a silicon die including a first planar surface comprising a base substrate and a second planar surface comprising a plurality of connection terminals defining a connection plane; b) a planar capacitor with a top surface positioned adjacent to the first planar surface of the silicon die and including a first charge accumulation plate and a second charge accumulation plate separated by a dielectric; and c) a first via structure extending from the top surface of the capacitor to the connection plane and electrically coupling the first charge accumulation plate to a connection terminal in the connection plane. The second charge accumulation plate may be electrically coupled to the base substrate. Preferably, the plurality of connection terminals are controlled collapse chip connection terminals.
The integrated circuit may further include a second via structure extending from the top surface of the capacitor to the connection plane and electrically coupling the second charge accumulation plate to a connection terminal in the connection plane. Again, The second charge accumulation plate may be electrically coupled to the base substrate and the plurality of connection terminals may be controlled collapse chip connection terminals (C
4
).
A second object of the present invention is to provide a capacitor structure comprising: (a) a capacitor including a first planar charge accumulation plate and a second planar charge accumulation plate separated by a dielectric; (b) a first via support structure extending from a top surface of the capacitor to a connection plane and including a first controlled collapse chip connection (C
4
) terminal positioned in the connection plane and a via coupling the first planar charge accumulation plate to the first controlled collapse chip connection terminal (C
4
); and (c) a second via support structure spaced apart from the first via support chip and extending from the top surface of the capacitor to the connection plane and including a second controlled collapse chip connection (C
4
) terminal positioned in the connection plane and a via coupling the second planar charge accumulation plate to the second controlled collapse chip connection terminal (C
4
).
The capacitor structure may further include a logic circuit fabricated on a silicon die and positioned adjacent to the top surface of the capacitor between of the first via support structure and the second via support structure and including a plurality of logic circuit controlled collapse chip connection (C
4
) terminals positioned in the connection plane. Further yet the structure may include a ball grid array mounting base including a ground trace coupling to the silicon die and to the first via support structure and a Vdd trace coupling to the silicon die and to a second via support structure. Alternatively, the structure may include a printed circuit board mounting base including a ground trace coupling to the silicon die and to the first via support structure and a Vdd trace coupling to the silicon die and to a second via support structure.
A third object of the present invention is to provide a method of fabricating an integrated circuit structure, comprising: (a) fabricating a planar capacitor with a first charge accumulation plate and a second charge accumulate plate separated by a dielectric; (b) fabricating a first interconnect via extending from the capacitor to a connection plane and including a first conductive via for coupling the first charge accumulation plate to a terminal in the connection plane; (c) fabricating a second interconnect via extending from the capacitor to the connection plane and including a second conductive via for coupling the second charge accumulation plate to a terminal in the connection plane; (d) fabricating a semiconductor logic circuit on a silicon die with a bottom side adjacent to a top side of the capacitor and a top side extending to the connection plane; and (e) fabricating a plurality of connection terminals on the top surface of the semiconductor logic circuit.
Such method may further include fabricating an IC package including a plurality of vias, each corresponding to one of said connection terminals and simultaneously bonding the capacitor and the silicon die to the IC package to conductively couple the each of said connection terminals to one of said plurality of vias. Alternatively, such method may further include fabricating a printed circuit board including a plurality of vias, each corresponding to one of said connection terminals and simultaneously bonding the capacitor and the silicon die to the IC package to conductively couple the each of said connection terminals to one of said plurality of vias.
REFERENCES:
patent: 5144526 (1992-09-01), Vu et al.
patent: 5472900 (1995-12-01), Vu et al.
patent: 5770875 (1998-06-01), Assaderaghi et al.
patent: 5811868 (1998-09-01), Bertin et al.
patent: 5841182 (1998-11-01), Linn et al.
patent: 5920102 (1999-07-01), Davies et al.
patent: 5950292 (1999-09-01), Dimos et al.
patent: 5965917 (1999-10-01), Maszara et al.
patent: 6080620 (2000-06-01), Jeng
patent: 6096584 (2000-08-01), Ellis-Monaghan et al.
patent: 6188122 (2001-02-01), Davari et al.
patent: 6232154 (2001-05-01), Reith et al.
patent: 6271074 (2001-08-01), Hain et al.
patent: 6184567 (2002-02-01), Fujisawa et al.
patent: 410092966 (1998-04-01), None
Claims from Serial No. 09/510,833, filed Feb. 23, 2000.
Advanced Micro Devices , Inc.
Chambliss Alonzo
Renner , Otto, Boisselle & Sklar, LLP
Talbott David L.
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