Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2003-10-21
2009-02-24
Gurley, Lynne A. (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S777000, C257S723000, C257S783000, C257S786000, C257S778000, C257S773000, C257S776000, C257SE23021, C257SE23031, C257SE23048
Reexamination Certificate
active
07495326
ABSTRACT:
An electronic device may include first, second, and third substrates wherein the second electronic substrate is between the first and second electronic substrates. A first electrical and mechanical connection may be provided between the first and third electronic substrates, and a second electrical and mechanical connection may be provided between the second and third electronic substrates. In addition or in an alternative, an electronic device may include a printed circuit board, a first electronic substrate on the printed circuit board, a second electronic substrate on the first electronic substrate, and a third electronic substrate on the second electronic substrate. More particularly, the first electronic substrate may be between the printed circuit board and the second electronic substrate, and the second electronic substrate may be between the first and third electronic substrates. In addition, the second electronic substrate may be offset relative to the first and third electronic substrates so that a first end of the second electronic substrate extends beyond the first and third electronic substrates and so that the first and third electronic substrates extend beyond a second end of the second electronic substrate.
REFERENCES:
patent: 3105869 (1963-10-01), Branch et al.
patent: 3501681 (1970-03-01), Weir
patent: 3663184 (1972-05-01), Wood et al.
patent: 3760238 (1973-09-01), Hamer et al.
patent: 3770874 (1973-11-01), Krieger et al.
patent: 3871014 (1975-03-01), King et al.
patent: 3897871 (1975-08-01), Zimnbauer
patent: 3942187 (1976-03-01), Gelsing et al.
patent: 4074342 (1978-02-01), Honn et al.
patent: 4113578 (1978-09-01), Del Monte
patent: 4382517 (1983-05-01), Welsch
patent: 4473263 (1984-09-01), Sunstein
patent: 4532576 (1985-07-01), Reimer
patent: 4657146 (1987-04-01), Walters
patent: 4855809 (1989-08-01), Malhi et al.
patent: 4948754 (1990-08-01), Kondo et al.
patent: 4950623 (1990-08-01), Dishon
patent: 4962058 (1990-10-01), Cronin et al.
patent: 5022580 (1991-06-01), Pedder
patent: 5113314 (1992-05-01), Wheeler et al.
patent: 5160409 (1992-11-01), Moore et al.
patent: 5162257 (1992-11-01), Yung
patent: 5194137 (1993-03-01), Moore et al.
patent: 5239447 (1993-08-01), Cotues et al.
patent: 5240881 (1993-08-01), Cayetano et al.
patent: 5250843 (1993-10-01), Eichelberger
patent: 5289925 (1994-03-01), Newmark
patent: 5293006 (1994-03-01), Yung
patent: 5327013 (1994-07-01), Moore et al.
patent: 5327327 (1994-07-01), Frew et al.
patent: 5335795 (1994-08-01), Chizen
patent: 5347428 (1994-09-01), Carson et al.
patent: 5354711 (1994-10-01), Heitzmann et al.
patent: 5406701 (1995-04-01), Pepe et al.
patent: 5424920 (1995-06-01), Miyake
patent: 5432729 (1995-07-01), Carson et al.
patent: 5453582 (1995-09-01), Amano et al.
patent: 5616962 (1997-04-01), Ishikawa et al.
patent: 5680296 (1997-10-01), Hileman et al.
patent: 5739053 (1998-04-01), Kawakita et al.
patent: 5744382 (1998-04-01), Kitayama et al.
patent: 5751556 (1998-05-01), Butler et al.
patent: 5760478 (1998-06-01), Bozso et al.
patent: 5793116 (1998-08-01), Rinne et al.
patent: 5963793 (1999-10-01), Rinne et al.
patent: 5977640 (1999-11-01), Bertin et al.
patent: 6082610 (2000-07-01), Shangguan et al.
patent: 6369448 (2002-04-01), McCormick
patent: 6388333 (2002-05-01), Taniguchi et al.
patent: 6392292 (2002-05-01), Morishita
patent: 6563205 (2003-05-01), Fogal et al.
patent: 6621155 (2003-09-01), Perino et al.
patent: 6627980 (2003-09-01), Eldridge
patent: 6731009 (2004-05-01), Jones et al.
patent: 6768208 (2004-07-01), Lin et al.
patent: 6900528 (2005-05-01), Mess et al.
patent: 2002/0005577 (2002-01-01), Shimoda
patent: 2003/0122240 (2003-07-01), Lin et al.
patent: 2005/0146010 (2005-07-01), Moden et al.
patent: 1 248 295 (2002-10-01), None
patent: 2 688 628 (1993-09-01), None
patent: 55-111127 (1980-08-01), None
patent: 57-73952 (1982-05-01), None
patent: 57-197838 (1982-12-01), None
patent: 58-92230 (1983-01-01), None
patent: 58092230 (1983-01-01), None
patent: 59-154041 (1984-09-01), None
patent: 6-116552 (1986-01-01), None
patent: 63-222245 (1988-09-01), None
patent: 63-222445 (1988-09-01), None
patent: 4-150033 (1992-05-01), None
International Search Report for PCT/US 03/33211.
Howell et al: “Area Array Solder Interconnection Technology for the Three-Dimensional Silicon Cube”, Proceedings of the 1995 45thElectronic Components & Technology Conference, pp. 1174-1178.
Lineback, “3D IC Packaging Moves Closer to Comercial Use”, Electronic World News, May 21, 1990, p. 15.
Gurley Lynne A.
Im Junghwa
Myers Bigel & Sibley & Sajovec
Unitive International Limited
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