Coded data generation or conversion – Analog to or from digital conversion – Digital to analog conversion
Reexamination Certificate
1999-06-10
2001-03-20
Young, Brian (Department: 2819)
Coded data generation or conversion
Analog to or from digital conversion
Digital to analog conversion
Reexamination Certificate
active
06204790
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to digital-to-analog converters, and to methods of performing digital-to-analog conversion.
BACKGROUND OF THE INVENTION
Some digital-to-analog converters (DAC) take baseband digital samples and convert them to an IF (intermediate frequency) analog signal. The particular IF is determined by the frequency of a clock applied to the DAC. The spectrum of the analog signal is centred at the intermediate frequency, and typically drops off on either side of the intermediate frequency. All DACs introduce an interference effect known as spurs. These are spikes in the frequency domain representation of the converted signal which are caused by the design of the DAC, and may be a function of the clock, and certain input signal characteristics for example. While the maximum meaningful output of a DAC is determined by the number of bits in the DAC, the minimum is determined by the magnitude of the spurs. The SFDR (spurious free dynamic range) of the DAC is the maximum meaningful output minus the maximum spur magnitude, this representing the range of signal magnitudes to which the spurs contribute negligibly. It is a characteristic of existing DACs that the SFDR decreases with increasing frequency, and this limits the maximum frequency for which a given DAC will be useful. One result of this is that state of the art DACs do not have a sufficient SFDR for wideband/multi-carrier next generation wireless systems.
SUMMARY OF THE INVENTION
It is an object of the invention to obviate or mitigate one or more of the above identified disadvantages.
An apparatus for performing digital-to-analog conversion with an increased SFDR is provided. An incoming M-bit sample is split into first and second N-bit samples. Preferably, M=16, and N=12. The first N-bit sample contains information relating to the M-bit sample when outside a first predetermined range, and the second N-bit sample contains information relating to the M-bit sample when inside the first predetermined range. A first DAC processes the first N-bit sample to produce a first analog signal, and a second DAC for processing the second N-bit sample to produce a second analog signal. An attenuator attenuates the second analog signal to produce a third analog signal. Finally, a summer is provided for adding the first analog signal to the third analog signal representative of the M-bit sample. Preferably, the second predetermined range is a range having a size equal to the range of the second N-bit DAC which is centred at the midpoint of the range the M-bit sample.
Advantageously, most transitions in the signal occur in the second analog signal, and as such there is more noise in the second analog signal. However, the second analog signal is the signal which is attenuated, and this attenuation also attenuates the noise in the second analog signal. Thus, when the two analog signals are combined, a lower overall noise level results. The result is a digital-to-analog converter apparatus which is suitable for wideband applications which require large SFDR.
REFERENCES:
patent: 4198622 (1980-04-01), Connolly, Jr. et al.
patent: 4746903 (1988-05-01), Czarniak et al.
patent: 5294927 (1994-03-01), Levinson et al.
patent: 5894497 (1999-04-01), Overton
patent: 6097324 (2000-08-01), Myer et al.
Jin Hang
Teo Koon H.
Nortel Networks Limited
Young Brian
LandOfFree
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