Stacked die semiconductor package

Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip

Reexamination Certificate

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Details

C257S686000, C257SE25005, C257SE25006, C257SE25021, C257SE25027, C257SE23085

Reexamination Certificate

active

07605476

ABSTRACT:
A stacked die semiconductor package includes: a substrate, having a first surface and an opposite surface thereto; a plurality of dice, structured for being stacked one on top of the other on the first surface of the substrate, including at least a first die which is mounted closest to the first surface, a second die mounted thereupon and having a larger footprint area than the first die, and a top die having a smaller footprint area than the underlying die thereof, and each having a plurality of contact pads and a plurality of wires for electrically connecting the dice to the first surface of the substrate; at least one interposer between the plurality of dice; advantageously, said top die is electrically directly connected to one of the underlying dice. A method for the assembly of a stacked die semiconductor package is provided.

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patent: 2000307057 (2000-11-01), None
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patent: 03061006 (2003-07-01), None

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