Stacked die package

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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Details

C257S678000, C257S777000, C257S778000, C257SE25013, C257SE25018, C257SE25027, C257SE21614

Reexamination Certificate

active

08044497

ABSTRACT:
The formation of electronic assemblies is described. One embodiment includes first and second semiconductor die structures each including a front side and a backside, the front side including an active region and the backside including metal regions and non-metal regions thereon. The first and second semiconductor die structures include a plurality of vias, the vias forming electrical connections between the active region and the backside metal regions. The first and second semiconductor die structures are stacked together with at least one of the metal regions on the backside of the first semiconductor die structure in direct contact with at least one of the metal regions on the back side of the second semiconductor die structure. Other embodiments are described and claimed.

REFERENCES:
patent: 5902118 (1999-05-01), Hubner
patent: 6080640 (2000-06-01), Gardner et al.
patent: 6682955 (2004-01-01), Cobbley et al.
patent: 7217631 (2007-05-01), Suga
patent: 7279795 (2007-10-01), Periaman et al.
patent: 7400033 (2008-07-01), Cheah et al.
patent: 2001/0033030 (2001-10-01), Leedy
patent: 2008/0150155 (2008-06-01), Periaman et al.
patent: 2008/0237310 (2008-10-01), Periaman et al.
patent: 2008/0315388 (2008-12-01), Periaman et al.
patent: 2008/0315421 (2008-12-01), Periaman et al.
Shigetou et al., “Bumpless Interconnect Through Ultrafine Cu Electrodes by Means of Surface-Activated Bonding (SAB) Method”, IEEE Transactions on Advanced Packaging, vol. 29, No. 2, May 2006, pp. 218-226.

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