Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2000-04-26
2002-09-10
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S723000, C257S778000, C257S784000, C257S783000, C257S730000
Reexamination Certificate
active
06448659
ABSTRACT:
TECHNICAL FIELD
The present invention relates to semiconductor packaging technology. The present invention has particular applicability to semiconductor packages containing multiple semiconductor dies and to wire bonding stacked dies to substrates.
BACKGROUND ART
Ongoing advances in solid-state electronic devices impose continuous demands for integrated circuit devices with increased functionality, density, and performance. In response, multi-chip modules have evolved comprising a printed circuit board substrate to which a series of separate components are directly attached. Multi-chip devices advantageously increase circuit density with attendant improvements in signal propagation speed and overall device weight.
A conventional method of effecting electrical connection between a die and electric leads comprises wire bonding. Wire bonding techniques effect electrical interconnections among components in a discreet package by means of fine wire connectors welded to the individual components. Accordingly, a fine wire conductor or bond wire has one end connected to an electrical lead on the substrate surface and the other end connected to an electrical contact or bond pad on the die or chip.
In fabricating conventional multi-chip modules or multi-chip packages, semiconductor dies are superimposed, with the upper die typically overlapping at least one side surface of the underlying die. Overlapping portions of the upper die extending beyond or overhanging the side surfaces of the lower die contain bond pads on the upper surface to which bond wires are wire bonded.
For example, a conventional multi-die structure is schematically illustrated in
FIGS. 1 and 2
, wherein similar elements are denoted by similar reference numerals. Adverting to
FIG. 1
, substrate
10
has mounted thereon in a conventional manner first die
11
and second die
12
positioned above first die
1
such that overlapping parts
12
A and
12
B of second die
12
extend beyond the side surfaces of first die
11
A and
11
B, respectively. Bond pads
13
on the upper surface of first die
11
are electrically connected to conductors
16
on substrate
10
by wire bonds
15
. Bond pads
14
on the upper surface of overlapping portions
12
A and
12
B of upper die
12
are connected to conductors
16
by wire bonds
15
. Typically, the upper die
12
is positioned on first die
11
with a dielectric bonding material
20
, such as an epoxy resin, therebetween, as shown in FIG.
2
. Bond pad
14
on overlapping part
12
A extending beyond the side surface
11
A of underlying die
11
is wire bonded to a contact (not shown) on the main surface of substrate
10
with bond wire
15
, as illustrated in FIG.
2
. However, overlapping part
12
A of upper die
12
is not supported on its underside. Accordingly, upon wire bonding bond wire
15
to bond pad
14
on the overlapping part
12
A of upper die
12
, cracking occurs in upper die
12
, as indicated by arrow
21
, with an attendant decrease in the durability of the resulting packaged semiconductor device and/or increase in rejection rate.
Accordingly, there exists a need for a semiconductor package comprising a circuit assembly with stacked, offset dies exhibiting improved reliability and structural integrity. There also exists a need for a method of manufacturing a packaged semiconductor device comprising a circuit assembly with stacked, offset dies with improved reliability and structural integrity.
SUMMARY OF THE INVENTION
An advantage of the present invention is a circuit assembly comprising offsetting stacked dies exhibiting improved reliability and structural integrity.
Another advantage of the present invention is a method of manufacturing a circuit assembly comprising stacked upper and lower dies without cracking of an overlapping portion of the upper die during wire bonding.
Additional advantages and features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a circuit assembly comprising: a substrate comprising a main surface; a first die having an upper surface, a lower surface and side surfaces, the lower surface of the first die positioned on the main surface of the substrate; a resilient O-ring positioned around and adjacent the side surfaces of the first die; a second die, having an upper surface and a lower surface, positioned such that part of the second die is supported by the first die and another part of the second die overlaps a side surface of the first die and is supported by the resilient O-ring; a bond pad on the upper surface of the second die on the overlapping part supported by the resilient O-ring; and a bond wire connected to a conductor on the main surface of the substrate and wire bonded to the bond pad.
Another advantage of the present invention is a method of manufacturing a circuit assembly, the method comprising: providing a substrate having a main surface; positioning a first die, having an upper surface, a lower surface and side surfaces, such that the lower surface of the first die is on the main surface of the substrate; disposing a resilient O-ring around and adjacent the side surfaces of the first die; positioning a second die, having an upper surface and a lower surface, such that part of the second die is supported by the first die and another part of the second die overlaps a side surface of the first die and is supported by the resilient O-ring, the upper surface of the second die having a bond pad on the overlapping part supported by the resilient O-ring; and wire bonding a bond wire to the bond pad.
Embodiments of the present invention comprise dispensing a bonding material, such as a nonconductive epoxy resin, on the upper surface of the first die prior to positioning the second die thereon. Embodiments of the present invention further include positioning the second die overlapping at least two opposing side surfaces of the first die such that the overlapping parts of the second die are supported by a resilient elastomeric O-ring. A plurality of bond wires are wire bonded to the bond pads on each of the overlapping parts of the second die, the bond wires being connected to bond fingers or conductors on the main surface of the substrate.
Additional advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the present invention. As will be realized, the present invention is capable of other and different embodiments and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and descriptions are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5489804 (1996-02-01), Pasch
patent: 5721452 (1998-02-01), Fogal et al.
patent: 5963429 (1999-10-01), Chen
patent: 6100594 (2000-08-01), Fukui et al.
patent: 6147401 (2000-11-01), Solberg
Advanced Micro Devices , Inc.
Loke Steven
Parekh Nitin
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