Stacked dice standoffs

Details Stacked dice standoffs Stacked dice standoffs

2002-03-13

2004-06-22

Clark, S. V. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Ball or nail head type contact, lead, or bond

C257S777000

Reexamination Certificate

active

06753613

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to stacked dice packages and methods for fabricating the same. In particular, the present invention relates to standoffs of pillars positioned to separate microelectronic dice during fabrication of stacked dice packages.
2. State of the Art
Higher performance, reduced cost, increased miniaturization of integrated circuit components, and greater packaging densities of microelectronic devices are ongoing goals of the computer industry. One method of increasing the density of microelectronic device packages is to stack the individual microelectronic dice within the packages.
FIG. 19
illustrates an exemplary assembly
200
comprising a first microelectronic die
202
(such as a microprocessor, a chipset, a memory device, an ASIC, and the like) attached by a back surface
204
thereof to a substrate
212
(such as an interposer, a motherboard, a back surface of another microelectronic die, or the like) by a first layer of adhesive
214
. A plurality of bond pads
216
is disposed on an active surface
206
of the first microelectronic die
202
. The first microelectronic die bond pads
216
are generally placed near edges of the first microelectronic die active surface
206
and are electrically connected by a first plurality of bond wires
218
to corresponding first plurality of lands
222
on a surface
224
of the substrate
212
.
A second microelectronic die
232
is attached by a back surface
234
thereof to the first microelectronic die active surface
206
. A plurality of bond pads
242
is disposed on an active surface
236
of the second microelectronic die
232
. The second microelectronic die bond pads
242
are generally placed near edges of the second microelectronic die active surface
236
and are electrically connected by a second plurality of bond wires
244
to a second plurality of lands
246
on the substrate surface
224
. The first plurality of substrate lands
222
and the second plurality of substrates lands
246
are generally connected to conductive traces (not shown) that are in contact with external electrical connection devices, such as solder ball or pins (not shown), which connect the assembly
200
to external electrical devices (not shown).
When the second microelectronic die
232
is about the same size or larger than the first microelectronic die
202
, such that the first plurality of wire bonds
218
may be contacted by the second microelectronic die
232
, a standoff is necessary to raise the second microelectronic die
232
above the first microelectronic die
202
to give clearance for the first plurality of wire bonds
218
. As shown in
FIG. 17
, a thick layer of die attach adhesive
252
(such as epoxies, urethane, polyurethane, silicone elastomers, and the like) may be disposed between the first microelectronic die active surface
206
and the second microelectronic die back surface
234
. Thereafter, an encapsulation material
254
is disposed to cover the first microelectronic die
202
and the second microelectronic die
232
.
One problem that must be addressed in the connection of various different types of materials (i.e., microelectronic dices, adhesives, encapsulation materials, etc.) is the coefficient of thermal expansion (“CTE”) for each material. The CTE is a measurement of the expansion and contraction of each material during heating and cooling cycles, respectively. These heating and cooling cycles occur during the operation of the microelectronic device
202
and during power up and power down of the microelectronic device
202
.
The use of a thick die attach adhesive layer
252
can cause stresses due to a mismatch between the CTE of the thick die attach adhesive layer
252
and the microelectronic dice (first microelectronic die
202
and second microelectronic die
232
) as the assembly
200
heats to a normal operating temperature when on and room temperature when off. Furthermore, materials used for the thick die attach adhesive layer
252
generally shrink during the curing process, which also places stresses on the first microelectronic die
202
and the second microelectronic die
232
. Stresses due to CTE mismatch and curing increase the probability that cracks will initiate and propagate in both the first microelectronic die
202
and the second microelectronic die
232
. These cracks may cause the failure of the first microelectronic die
202
and/or the second microelectronic die
232
.
Another problem with thick die attach adhesive layers
252
is their tendency to absorb moisture, which can have adverse affects on the first microelectronic die
202
and the second microelectronic die
232
. A further problem is proper flow control of the adhesive material. Improperly applied adhesive can interfere with the first plurality of bond wires
218
and first plurality of bond pads
216
.
As shown in
FIG. 20
, to overcome for the problems with the use of thick die attach adhesive layers
252
(see FIG.
19
), a spacer
266
(such as silicon, having about the same CTE as the first microelectronic die
202
and the second microelectronic die
232
) may be attached to the first microelectronic die active surface
206
with a first, thin die spacer adhesive layer
262
and attached to the second microelectronic die back surface
234
with a second, thin die spacer adhesive layer
264
to form a package
270
. However, using the spacer
262
involves additional processing steps and presents alignment problems, which increases the cost of the package
270
.
Furthermore, with both packages described above, the CTE can cause delamination between the adhesive layers and the microelectronic dice.
Therefore, it would be advantageous to develop a stacked package providing adequate spacing between the stacked microelectronic dice that does not have the disadvantages of thick adhesive layers or of spacers.


REFERENCES:
patent: 5818107 (1998-10-01), Pierson et al.
patent: 5872400 (1999-02-01), Chapman et al.
patent: 6169328 (2001-01-01), Mitchell et al.
patent: 6175157 (2001-01-01), Morifuji
patent: 6184062 (2001-02-01), Brofman et al.
patent: 6184582 (2001-02-01), Coult et al.
patent: 6238949 (2001-05-01), Nguyen et al.
patent: 6271598 (2001-08-01), Vindasius et al.
patent: 6313998 (2001-11-01), Kledzik et al.
patent: 6392304 (2002-05-01), Butler
patent: 6472758 (2002-10-01), Glenn et al.

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