Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Having air-gap dielectric
Patent
1998-04-01
2000-02-01
Dang, Trung
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Having air-gap dielectric
438589, 438409, 438408, H01L 2176
Patent
active
060202505
ABSTRACT:
Chips having subsurface structures within or adjacent a horizontal trench in bulk single crystal semiconductor are presented. Structures include three terminal devices, such as FETs and bipolar transistors, rectifying contacts, such as pn diodes and Schottky diodes, capacitors, and contacts to and connectors between devices. FETs have low resistance connectors to diffusions while retaining low overlap capacitance. A low resistance and low capacitance contact to subsurface electrodes is achieved by using highly conductive subsurface connectors which may be isolated by low dielectric insulator. Stacks of devices are formed simultaneously within bulk single crystal semiconductor. A subsurface CMOS invertor is described. A process for forming a horizontal trench exclusively in heavily doped p+ regions is presented in which porous silicon is first formed in the p+ regions and then the porous silicon is etched.
REFERENCES:
patent: 3919060 (1975-11-01), Pogge et al.
patent: 4104090 (1978-08-01), Pogge
patent: 5057450 (1991-10-01), Bronner et al.
patent: 5306659 (1994-04-01), Beyer et al.
Dang Trung
International Business Machines - Corporation
Leas James M.
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