Stacked device assembly

Details Stacked device assembly Stacked device assembly

2002-12-03

2004-04-20

Tolin, G. (Department: 2835)

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

C257S686000, C257S777000, C361S719000, C361S735000

Reexamination Certificate

active

06724630

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a stacked device assembly. In particular, the present invention relates to a stacked electronic device in which two electronic devices are stacked one on top the other.
BACKGROUND OF THE INVENTION
In order to enhance a mounting density of electronic devices, in particular semiconductor devices on a substrate, there have been proposed a variety of stacking techniques so far. In addition, an idea might have been proposed in which two semiconductor devices are mounted one on top the other while leads of one device do not contact with those of the other. This arrangement can only be realized only when one semiconductor device is larger than the other. However, actually it has been required to stack two devices of substantially the same size. In this instance, if the devices have a flat package from which a plurality of leads are extended from its side and then bent downwardly, a precise arrangement of the devices in which no horizontal shift is made between the devices causes the leads of one device to contact with the leads of the other. The contacts may be prevented by extending a horizontal portion of the leads of the upper device, which in turn results in an increase of the mounted area of the devices.
To overcome this problem, JP 6-97355 (A) discloses another stacked electronic device which is illustrated in FIG.
5
and generally indicated by reference numeral U
3
. The stacked electronic device U
3
has a lower, package type semiconductor device
500
and an upper, package type semiconductor device
600
. Packages of those devices
500
and
600
have substantially the same size. Those devices
500
and
600
are stacked one on top the other so that each lead
501
,
502
. . . of the lower device
500
is positioned between the adjacent leads
601
,
602
. . . of the upper device
600
without any contact therewith. This arrangement does not need the upper leads
601
,
602
. . . to extend horizontally and outwardly.
As discussed above, although this arrangement is effective for preventing the enlargement of the upper device, it has another drawbacks which will be described with reference to FIG.
6
. As shown, two stacked electronic devices U
3
and U
4
are mounted on the substrate in a parallel fashion, and spaced L
2
. Also, leads from one device U
3
are opposed to those from the other device U
4
, leaving a first gap d therebetween defined by a clearance for absorbing dimensional errors caused at the manufacturing of the device and a second gap e, f determined by the horizontal length of the leads.
However, the arrangement needs one leads from the lower device
500
(
550
) to be positioned between adjacent leads of the upper device
600
(
650
). This might be done without any difficulty if the lower and the upper devices are the same. Actually, since a great number of flat package type electronic devices with different sizes are available, it is very difficult to identify which electronic device should be combined with which electronic device. Also, the gap between leads of one device should be larger than that of the other, which imposes a considerable restriction on the design of the leads and the device itself.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is to provide a stacked electronic device capable of overcoming such restrictions on the lead design and resulting in a variety of functional advantages over the conventional stacked electronic device.
To this end, an electronic device assembly of the present invention, comprising: a lower electronic device to be mounted on a substrate; and an upper electronic device to be provided on or above the lower electronic device, wherein the lower electronic device has a first package, the first package having a lower surface and an upper surface, the lower surface bears a plurality of electrodes so that the electrodes exist within a region defined by the lower surface, wherein the lower electronic device is mounted on the substrate so that the electrodes contact with the substrate; wherein the upper electronic device has a second package and a plurality of leads each extending from the second package toward the substrate, wherein the upper electronic device is provided on or above the lower electrodes while the leads contact with the substrate.
In another aspect of the invention, each electrode has a solder ball.
In another aspect of the invention, each lead of the upper electronic device extends from a side of the second package and then turns toward the substrate.
In another aspect of the invention, the electronic device assembly also comprises a cooling member between the lower and upper electronic devices.
In another aspect of the invention, a substrate having at least two electronic device assemblies each of claim 1, wherein the assemblies are arranged so that each of their leads are positioned between adjacent assembly's leads, in a staggered fashion.
Further features and advantages of the present invention, as well as the structure and operation of various embodiments of the present invention, are described in detail below with reference to the accompanying drawings.
Also, the present application is based upon the Japanese Patent Application No. 2002-153577, the full disclosure of which is incorporated herein by reference.


REFERENCES:
patent: 5910685 (1999-06-01), Watanabe et al.
patent: 6028352 (2000-02-01), Eide
patent: 6031727 (2000-02-01), Duesman et al.
patent: 6461897 (2002-10-01), Lin et al.
patent: 6525943 (2003-02-01), Moden et al.
patent: 2-125648 (1990-05-01), None
patent: 2-130996 (1990-05-01), None
patent: 6-97355 (1994-04-01), None
patent: 9-283697 (1997-10-01), None
USPGPUB 2002/0181216 A1, Kledzik, May 6, 2002.*
U.S. patent application Ser. No. 09/947,360, filed Sep. 7, 2001 (Our Ref.: 50006-120).

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