Static information storage and retrieval – Interconnection arrangements
Reexamination Certificate
2005-04-19
2005-04-19
Nguyen, Viet Q. (Department: 2818)
Static information storage and retrieval
Interconnection arrangements
C365S046000, C365S051000, C365S072000, C365S100000, C365S148000, C365S189080
Reexamination Certificate
active
06882553
ABSTRACT:
This invention relates to a resistive memory array architecture which incorporates certain advantages from both cross-point and one transistor per cell architectures during reading operations. The fast read-time and higher signal to noise ratio of the one transistor per cell architecture and the higher packing density of the cross-point architecture are both exploited by using a single access transistor to control the reading of multiple stacked columns of resistive memory cells each column being provided in a respective stacked memory layer.
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Nejad Hasan
Seyyedy Mirmajid
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