Stacked chip structure and fabrication method thereof

Details Stacked chip structure and fabrication method thereof Stacked chip structure and fabrication method thereof

2008-08-25

2009-06-02

Hoang, Quoc D (Department: 2892)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257S777000, C257SE23085

Reexamination Certificate

active

07541217

ABSTRACT:
A fabrication method of a stacked chip structure is provided. Firstly, a first conductive layer is formed on a first surface of a wafer. Afterwards, a first patterned polymer layer is formed on the first conductive layer, and a second patterned polymer layer is formed on a second surface of the wafer. Next, a second conductive layer is electroplated on the first conductive layer and is heated to form a number of solder bumps. After that, the wafers are stacked on a substrate structure. The first patterned polymer layer disposed on a first wafer of the wafers is correspondingly connected to the second patterned polymer layer on a second wafer of the wafers. The present invention is suitable for the stacked chip structure connected by the fine-pitch solder bumps. Besides, the fabrication of the present invention is relatively simplified.

REFERENCES:
patent: 7151009 (2006-12-01), Kim et al.
patent: 2008/0073741 (2008-03-01), Apanius et al.

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