Stacked chip scale package

Details Stacked chip scale package Stacked chip scale package

2000-08-07

2002-04-02

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

For plural devices

C257S777000

Reexamination Certificate

active

06365966

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a stacked chip scale package. More particularly, the present invention relates to a stacked chip scale package capable of reducing package thickness and preventing any short-circuiting between conductive wires.
2. Description of Related Art
Advances in integrated circuit are made towards a higher level of integration, higher packing density, smaller volume, multi-functions and higher performance. All these improvements befall not just in the fabrication of semiconductor chip, but also in the later stage packaging of semiconductor chips as well. The up-coming trend is towards the fabrication of more multi-function high-performance integrated circuits. For example, a logic chip, a memory controller chip and a graphic accelerator chip are often integrated together in the same package so that a single package can perform multiple functions. In the semiconductor industry, the system-on-chip (SOC) package has been developed. However, bottlenecks in the fabrication of system chips still exist, creating a need for a breakthrough to increase production yield before mass production is feasible. Among the back-stage packaging techniques, multi-chip module (MCM) is the most promising technique for the future.
In a multi-chip module, a plurality of silicon chips is sealed within the same package. Compared with various individually packaged chips, a MCM is much better at reducing package volume and shortening signal transmission route between different chips.
FIG. 1
is a schematic cross-sectional view showing a conventional multi-chip module.
FIG. 2
is a top view of the multi-chip module shown in FIG.
1
. As shown in
FIGS. 1 and 2
, a conventional multi-chip module
100
is built atop a laminated board
102
. Laminated board
102
consists of a plurality of patterned wiring layers and insulation layers (not shown) alternating with each other. The upper surface
102
a
of laminated board
102
includes a plurality of mounting pads or gold fingers
104
. The backsides
110
b
and
120
b
of chips
110
and
120
are attached to the upper surface
102
a
of laminated board
102
with an adhesive material
140
. The active surface
110
a
of chip
110
has a plurality of bonding pads
112
and the active surface
120
a
of chip
120
has a plurality of bonding pads
122
. The bonding pads
112
and
122
serve as contact nodes for external devices. Gold wires
142
are used to connect bonding pads
112
and
122
with mounting pads
104
. A molding compound
144
encloses the gold wires
142
, the chips (
110
and
120
) and a portion of the laminated layer
102
. A plurality of solder balls
146
is attached to the underside
102
b
of laminated board
102
, thereby forming a ball grid array (BGA). Solder balls
146
connect with mounting pads using patterned wiring layers and serve as external contact nodes for multi-chip module
100
. The solder balls of the multi-chip module can be soldered onto a printed circuit board using surface mount technologies.
The aforementioned multi-chip module employs a side-by-side layout design. Hence, area occupation is somewhat larger and packing density is somewhat lower than in a chip scale package (CSP).
FIG. 3
is a schematic cross-sectional side view of a conventional stacked chip scale package. As shown in
FIG. 3
, a conventional stacked chip scale package (SCSP)
200
is built atop a laminated board
202
. A plurality of mounting pads
204
is formed on the upper surface
202
a
of laminated board
202
. The backside
210
b
of a silicon chip
210
is attached to the upper surface
202
a
of laminated board
202
with an adhesive material
240
. The backside
220
b
of a silicon chip
220
is attached to the active surface
210
a
of chip
210
with the adhesive material
240
, thereby forming a stacked structure. The active surfaces
210
a
of chip
210
has a plurality of bonding pads
212
and the active surface
220
a
of silicon chip
220
has a plurality of bonding pads
222
. The bonding pads
212
and
222
serve as contact nodes for external devices. Gold wires
242
and
244
are used to connect mounting pads
204
with bonding pads
220
and
210
respectively. A molding compound
246
encloses the gold wires (
242
and
244
), the chips (
210
and
220
) and a portion of the laminated layer
202
. A plurality of solder balls
248
is attached to the underside
202
b
of laminated board
202
, thereby forming a ball grid array (BGA). Solder balls
248
connect with mounting pads is
204
using patterned wiring layers and serve as external contact nodes for stacked chip scale package
200
. The solder balls of the chip scale package can be soldered onto a printed circuit board using surface mount technologies. Although the chip scale package can reduce area occupation and considerably increase packing density, arching gold wires
242
and
244
above silicon chips
210
often lead to short-circuiting.
SUMMARY OF THE INVENTION
The present invention provides a stacked chip scale package capable of preventing the short-circuiting of connection wires going to two separate silicon chips inside the package so that production yield is increased.
The invention further provides a stacked chip scale package capable of reducing overall package thickness.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a stacked chip scale package. The stacked chip scale package uses a substrate having mounting pads thereon. The mounting pads are arranged to lie close to the rectangular sides. A lower and an upper chip are stacked on top each other above the substrate. The chip sitting directly on top of the substrate has a larger size. The upper chip rests on the active surface of the lower chip. The mounting pads on the substrate are distributed around the periphery of the lower silicon chip. Both the upper chip and the lower chip have only one pair of opposite sides having bonding pads. The pair of opposite edges of the upper silicon chip having bonding pads is parallel to the pair of opposite edges of the lower silicon chip without bonding pads. The bonding pads on the upper chip and the lower chip are electrically connected to their neighboring mounting pads using conductive wires. Molding compound encloses the conductive wires, the upper silicon chip, the lower chip and a portion of the substrate.
According to one embodiment of this invention, distance between the bonding pads of the lower chip and neighboring mounting pad is about 15-30 mils. The difference in distance between separation of bonding pads on opposite edges of the upper chip and separation of bonding pads on the opposite edges of the lower chip is greater than 200 mils. In addition, the bonding pads on the upper chip and the mount pad are wire bonded together using a reverse bonding method so that overall thickness of the package can be further reduced.
In this invention, the pair of opposite sides with bonding pads on the upper chip is orthogonal to the pair of opposite sides with bonding pads on the lower chip. The mounting pads corresponding to the bonding pads are formed on four sides of the substrate. Furthermore, for a stacked structure having an upper silicon chip much smaller than the lower silicon chip, orthogonal distribution of bonding pads on opposite sides can prevent the short-circuiting of conductive wire leading from bonding pads. Moreover, the stacked structure of this invention can reduce length of bonding wires, thereby lowering arc height of bonding wires and hence overall package thickness.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5721452 (1998-02-01), Fogal et al.
patent: 6133637 (2000-10-01), Hikita et al.

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