Stacked chip-packaging structure

Details Stacked chip-packaging structure Stacked chip-packaging structure

2006-04-11

2006-04-11

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S685000, C257S723000, C257S784000, C257S777000, C257S733000, C257S787000

Reexamination Certificate

active

07026709

ABSTRACT:
A stacked chip-packaging structure consisting of a plurality of chip-packaging units is provided. Each of the chip-packaging units includes a substrate, a chip, a plurality of wires, a molding compound, and a plurality of solder balls. The chip-packaging units are, for example, of a BGA structure with high pin count, and are stacked up one over another and electrically connected through solder balls. With such structural features, the space that the stacked chip-packaging structure occupies is reduced and consequently the entire structure can be miniaturized.

REFERENCES:
patent: 5783870 (1998-07-01), Mostafazadeh et al.
patent: 5962810 (1999-10-01), Glenn
patent: 6025648 (2000-02-01), Takahashi et al.
patent: 6166444 (2000-12-01), Hsuan et al.
patent: 6586832 (2003-07-01), Shibata et al.
patent: 6653723 (2003-11-01), Manansala

Affiliated with

Also associated with

Rating

Stacked chip-packaging structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Stacked chip-packaging structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked chip-packaging structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3597578