Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Chip mounted on chip
Reexamination Certificate
2002-05-28
2004-11-16
Thai, Luan (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Chip mounted on chip
C257S784000, C257S723000, C257S686000
Reexamination Certificate
active
06818998
ABSTRACT:
BACKGROUND
1. Field of the Invention
The present invention relates to stacked chip packaging technology. More particularly, the present invention relates to a stacked chip package that includes an upper chip having trenches and a method of manufacturing the same.
2. Description of the Related Art
As more circuitry is integrated into high performance semiconductor chips, the size of such chips increases and the need for a greater density of chips is needed. Stacked chip packages and stacked packages have been developed to meet this need. Stacked chip packages include multiple chips stacked on one another and embodied in a single package. In contrast, stacked packages includes multiple packages, where each package includes a single chip, stacked on one another. Stacked chip packages and stacked packages have the advantage that chips having several functions can be embodied in a single package.
In a stacked package, the thickness of an individual package is at least two times that of the chip embodied within the package. Thus as individual packages are stacked to form a stacked package, the thickness of the resulting stacked package is very thick which is undesirable. Also, to electrically connect the individual packages, the leads which extend from each package must be deformed. This requires additional steps to be performed when fabricating a stacked package which can decrease yield. Such steps can include fitting the external lead of the individual package disposed in the upper portion into the external lead of the individual package disposed in the lower portion, and punching in the external lead of the individual stacked package perpendicularly, and inserting a connecting terminal in the hole or other suitable deformation. Since an external connection terminal must be used in a stacked package, a decrease of the yield of the such packages is inevitable.
When compared to stacked packages, stacked chip package are more advantageous since they can be mounted more easily and effectively. Additionally, stacked chip packages can be designed using different types of internal structures.
For example, one conventional stacked chip package includes a lower chip which is attached to a lower surface of a lead frame die pad via an adhesive, and an upper chip which is attached to the upper surface of the die pad via an adhesive. The lower chip is attached to the die pad such that the active surface of the lower chip faces downward, and the upper chip is attached to the die pad such that the active surface of the upper chip faces upward. The upper and lower semiconductor chips respectively are electrically connected to a lead frame via bonding wires. The upper and lower chips and the bonding wires are encapsulated and protected by a package body formed by a mold resin. In this type of conventional stacked chip package, the lower chip and the upper chip can have the same size and be identical to one another. For example, the upper and lower chips can both be edge pad chips, on which electrode pads connected to the bonding wires are formed in the edge portion of the active surface of the chip.
Another conventional stacked chip package is configured to stack a plurality of chips on a die pad in the same direction. In such a case, a lower chip must be larger than an upper chip. The lower chip is attached to the die pad via an adhesive and the upper chip is attached to the active surface of the lower chip via an adhesive. The upper and lower chips are electrically connected to leads via bonding wires, and are protected by a package molding body. In the stacked package having the above-described structure, the structures of the upper and lower chips must be different from each other (i.e., the lower chip must be larger than the upper chip).
SUMMARY
In one embodiment of the present invention, a stacked chip package is provided. The stacked chip package includes a substrate having an upper surface and a lower surface, a first semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the first semiconductor chip is attached to the upper surface of the substrate and the upper surface of the first semiconductor chip includes a plurality of first electrode pads, and a second semiconductor chip having an upper surface and a lower surface, wherein the lower surface of the second semiconductor chip is attached to the upper surface of the first semiconductor chip and the lower surface of the second semiconductor chip includes trenches that correspond to the locations of the first electrode pads on the upper surface of the first semiconductor chip.
Other embodiments, aspects, and advantages of the present invention will become apparent from the following descriptions and the accompanying drawings.
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Kang Sa Yoon
Kwon Yong Hwan
Oh Se Yong
Harness Dickey
Mitchell James M.
Thai Luan
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