Stacked chip electronic package having laminate carrier and...

Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices

Reexamination Certificate

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Details

C361S780000, C361S810000, C257S706000, C257S707000, C257S723000, C257S777000, C438S109000, C438S122000

Reexamination Certificate

active

11238960

ABSTRACT:
A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.

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