Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2007-01-09
2007-01-09
Reichard, Dean A. (Department: 2841)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S780000, C361S810000, C257S706000, C257S707000, C257S723000, C257S777000, C438S109000, C438S122000
Reexamination Certificate
active
11238960
ABSTRACT:
A multi-chip electronic package which utilizes an organic, laminate chip carrier and a pair of semiconductor chips positioned on an upper surface of the carrier in a stacked orientation. The organic, laminate chip carrier is comprised of a plurality of conductive planes and dielectric layers and couples one or both of the chips to underlying conductors on the bottom surface thereof. The carrier may include a high-speed portion to assure high-frequency connection between the semiconductor chips and may also include an internal capacitor and/or thermally conductive member for enhanced operational capabilities. The first chip, e.g., an ASIC chip, is solder bonded to the carrier while the second chip, e.g., a memory chip, is secured to the first chip's upper surface and coupled to the carrier using a plurality of wirebond connections.
REFERENCES:
patent: 4882454 (1989-11-01), Peterson et al.
patent: 4902610 (1990-02-01), Shipley
patent: 5072075 (1991-12-01), Lee et al.
patent: 5121190 (1992-06-01), Hsiao et al.
patent: 5336855 (1994-08-01), Kahlert et al.
patent: 5418690 (1995-05-01), Conn et al.
patent: 5483421 (1996-01-01), Gedney et al.
patent: 5574630 (1996-11-01), Kresge et al.
patent: 5615087 (1997-03-01), Wieloch
patent: 5661089 (1997-08-01), Wilson
patent: 5768109 (1998-06-01), Gulick et al.
patent: 5798563 (1998-08-01), Feilchenfeld et al.
patent: 5838063 (1998-11-01), Sylvester
patent: 5891869 (1999-04-01), Lociuro et al.
patent: 5894173 (1999-04-01), Jacobs et al.
patent: 5894517 (1999-04-01), Hutchison et al.
patent: 5900675 (1999-05-01), Appelt et al.
patent: 5926377 (1999-07-01), Nakao et al.
patent: 5982630 (1999-11-01), Bhatia
patent: 6023211 (2000-02-01), Somei
patent: 6075423 (2000-06-01), Saunders
patent: 6081430 (2000-06-01), La Rue
patent: 6146202 (2000-11-01), Ramey et al.
patent: 6222740 (2001-04-01), Bovensiepen et al.
patent: 6246010 (2001-06-01), Zenner et al.
patent: 6351393 (2002-02-01), Kresge et al.
patent: 6370012 (2002-04-01), Adae-Amoakoh et al.
patent: 6431914 (2002-08-01), Billman
patent: 6495772 (2002-12-01), Anstrom et al.
patent: 6841881 (2005-01-01), Katagiri et al.
patent: 2002/0125967 (2002-09-01), Garrett et al.
patent: 1-307294 (1989-12-01), None
patent: 4025155 (1992-01-01), None
patent: 6112271 (1994-04-01), None
patent: 9-232376 (1997-09-01), None
patent: 10-209347 (1998-08-01), None
patent: 11-087560 (1999-03-01), None
patent: 2000-022071 (2000-01-01), None
patent: 2000-024150 (2000-01-01), None
IBM TDB, “Multi Chip Cooling Plate”, Jul. 1978 pp. 745-746.
IBM TDB, “Simultaneous Chip Placement—Multi-Chip Modules”, Feb. 1982 pp. 4647-4649.
IBM TDB, “High Performance Multi-Chip Module”, Nov. 1987 pp. 437-439.
IBM TDB, “Low-Cost, High-Power, Multi-Chip Module Design”, Aug. 1988 pp. 451-452.
IBM TDB, “Thermally Conductive Substrate Mounted Multi-Chip Module Cap”, Sep. 1993 pp. 623-624.
Fraley Lawrence R.
Markovich Voya
Carpio Ivan H
Endicott Interconnect Technologies, Inc.
Fraley Lawrence R.
Hinman, Howard & Kattell LLP
Reichard Dean A.
LandOfFree
Stacked chip electronic package having laminate carrier and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked chip electronic package having laminate carrier and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked chip electronic package having laminate carrier and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3733800