Stacked chip assembly and manufacturing method therefor

Details Stacked chip assembly and manufacturing method therefor Stacked chip assembly and manufacturing method therefor

1991-07-09

1994-05-10

Picard, Leo P.

Electricity: electrical systems and devices

Housing or mounting assemblies with diverse electrical...

For electronic systems and devices

361744, 361748, 361772, 361777, 361813, 174255, 257686, H05K 702

Patent

active

053114019

ABSTRACT:
Two or more integrated circuit or memory chips (64-66, 104, 106-108, 116-118, 122-126) are stacked on a circuit substrate (72, 100) or a printed-wiring board in such a manner that the planes of the chips lie horizontally, rather than vertically, on the substrate or wiring board. The chips are preferably interconnected along all of their edges (68) and thence, preferably by ribbon bonds, to the substrate or wiring board. The thus assembled arrangement is hermetically sealed by coatings of passivation and encapsulant. Such chips (25) are oversized, as distinguished from chips conventionally diced from wafers. Specifically, each chip is larger than an individual wafer circuit (18, 20), that is, each wafer portion (24) which is selected to be formed into a chip has a size that is larger than the individual wafer circuit which it incorporates, thus overlapping adjacent circuits.

REFERENCES:
patent: 4567643 (1986-02-01), Droguet et al.

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