Stacked Charge pump circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

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Details

327537, 327589, 363 60, 307110, H01J 1982

Patent

active

059260599

ABSTRACT:
The invention relates to a voltage multiplier such as a charge pump circuit. The circuit is realized by a plurality of cascade connected voltage gain stages, each stage comprising a first and a second cell each receiving a pair of clock phase signals and comprising a pair of MOS transistors having first and second conduction terminals and a control terminal. These transistors have their first conduction terminals connected together and to a voltage reference; while the control terminals of each transistor are connected to the second conduction terminal of the other transistor of the same cell. Moreover, the second conduction terminal of the first transistor receives a first phase signal via a first coupling capacitor, and the second conduction terminal of the second transistor receives a second phase signals via a first pumping capacitor. Third and fourth cells are provided having the same structure as the first and the second cell. The third cell is coupled to the first cell by a series connection between their corresponding coupling capacitors and their corresponding pumping capacitors, respectively. The fourth cell is coupled to the second cell by a series connection between their corresponding coupling capacitors and by their corresponding pumping capacitors, respectively.

REFERENCES:
patent: 5126808 (1992-06-01), Montalvo et al.
patent: 5140182 (1992-08-01), Ichimura
patent: 5589793 (1996-12-01), Kassapian
John F. Dickson, "On-Chip High-Voltage Generation in MNOS Integrated Circuits Using an Improved Voltage Multipler Technique", IEEE Journal of Solid-State Circuits, vol. SC-11, No. 3, (Jun. 1976), pp. 374-378.

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