Stacked capacitors for VLSI semiconductor devices

Details Stacked capacitors for VLSI semiconductor devices Stacked capacitors for VLSI semiconductor devices

1990-05-08

1991-09-17

Prenty, Mark

357 41, 357 51, H01L 2968, H01L 2702

Patent

active

050499580

ABSTRACT:
A dynamic read/write memory cell array employs stacked capacitors consisting of three levels of conductor separated by dielectric material. In one embodiment, the central level is a common plane, and the upper and lower levels are connected to the source regions of the pair of access transistors of two adjacent cells. In this manner, capacitors for adjacent cells occupy the same area, almost doubling the capacitor value per unit area.

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K. Ohta, "VSLI Dynamic Memory Cell Using Stacked Ta.sub.2 O.sub.5 Capacitor", Semiconductor Technologies, 1982, pp. 280-284.
Koyanagi et al, "Novel High Density Stacked Capacitor MOS RAM", Japanese Journal of Appl. Physics, vol. 18 (1979), Supplement 18-1, pp. 35-42.

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