Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Reexamination Certificate
2000-08-03
2003-04-22
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
C438S253000, C438S586000, C438S618000, C438S622000, C438S637000, C438S639000
Reexamination Certificate
active
06551894
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a cell structure of dynamic RAM (i.e. DRAM), for example, more specifically, a STC (Stacked Capacitor)-type semiconductor storage device in which a memory cell capacitor is formed above a bit line so as to be self-aligned with the bit line, and relates to a manufacturing method thereof.
2. Description of the Related Art
Recently, a semiconductor storage device, particularly, a DRAM has been integrated greatly. Accordingly, a percentage of a unit storage element is showing a tendency to further increase. For this reason, a three-dimensional memory cell capacitor and a three-dimensional memory cell transistor are indispensable for obtaining enough capacity (not less than 20 fF) to read/write. As a result, a cell structure using a trench-type capacitor or STC-type capacitor is generally used.
In addition, in the cell using the STC-type capacitor, a technique for forming a memory cell capacitor so that it is self-aligned with a bit line is important to greater-scale integration. As a method of manufacturing the conventional STC-type capacitor, a memory cell is suggested as described in, for example, M. Fukumoto et al., “Stacked capacitor cell technology for 16M DRAM using double self aligned contacts”, ESSDERC 90, pp. 461-464, 1990.
FIGS. 13 through 15
show its example.
FIG. 13
shows a plan view of the memory cell. In
FIG. 13
,
201
is a channel region,
202
is a gate electrode pattern,
203
is a bit line contact,
204
is a bit line pattern,
205
is a storage node contact pattern, and
206
is a storage node electrode pattern.
FIGS. 14A through 14C
show manufacturing steps of a cross-sectional view taken along line
14
—
14
in FIG.
13
. As shown in
FIG. 14A
, an element separating oxide film
52
, a MOS transistor for transmitting data, not shown, a first inter-layer insulating film
53
, a bit line contact, not shown, a bit line
54
, and a second inter-layer insulating film
55
made of BPSG film are formed on a semiconductor substrate
51
. Next, a storage node contact
56
which reaches the semiconductor substrate
51
is formed in the first and second inter-layer insulating films
53
and
55
which is located between the bit lines
54
—
54
by the known lithography method and the RIE (Reactive Ion Etching) method.
Next, As shown in
FIG. 14B
, an HTO (High Temperature Oxide) film
57
is deposited over the whole surface, and the whole surface is etch-backed by the RIE method. Then, as shown in
FIG. 14C
, a side wall spacer
58
constituted by the HTO film
57
is formed on the first and second inter-layer insulating films exposed in the storage node contact
56
.
If the storage node contact pattern
205
shown in
FIG. 13
is not aligned with the bit line pattern
204
, the following problems arise. As shown in
FIG. 15A
, when the storage node contact
56
is formed, the bit line
54
is exposed from the first and second inter-layer insulating films
53
and
55
. In this state, as shown in
FIG. 15B
, the HTO film
57
is deposited on the whole surface, the whole surface is etch-backed by the RIE method. Then, as shown in
FIG. 15C
, the side wall spacer
58
is formed in the storage node contact
56
so as to be on the bit line
54
and the side wall of the second inter-layer insulating film
55
. However, since a part of the bit line
54
is exposed from a gap of the side wall spacer
58
, the storage node, not shown, which is formed later and the bit line
54
are short-circuited.
In addition, when the whole surface of the HTO film
57
is etch-backed, since the HTO film
57
and the second inter-layer insulating film
55
are made of silicon oxide, sufficient selectivity cannot be obtained. Therefore, it becomes difficult to control thicknesses of the insulating film on the bit line
54
and the second inter-layer insulating film
55
.
Furthermore, when the storage node contact
56
is formed, since a contact opening and a contact gap are minute, it is difficult to form a resist pattern. Moreover, the storage node contact
56
does not have a desired shape, i.e. square shape, and as shown by broken lines in
FIG. 13
, it has a circular shape. The circular shape has a diameter which is a minimum dimension of the diameter when the storage node contact
56
is inscribed in a square pattern. The contact area decreases, thereby increasing contact resistance. Moreover, since the storage node contact
56
reaches the semiconductor substrate
51
, an aspect ratio becomes large. As a result, yield of the contact opening is not efficient, and thus it is difficult to plug up the storage node.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor storage device which is capable of preventing a short-circuit of a contact and a wiring, forming the contact so that the contact is self-aligned, and securely controlling a thickness of a film formed on the wiring, forming a fine contact with an excellent yield of an opening of the contact, and filling up the contact, and relates to a manufacturing method thereof.
In order to achieve the above object, a semiconductor storage device of the present invention comprises:
a first insulating film formed on a semiconductor substrate;
first and second wirings arranged on the first insulating film at a predetermined interval, the first and second wirings composed of a conductive film, and a second insulating film on the conductive film;
a contact hole formed between the first and second wirings, and on the first insulating film between the first and second wirings; and
a third insulating film formed in the contact hole, the third insulating film being formed at least on a side wall of the conductive film and a side wall of the first insulating film.
In addition a method of manufacturing a semiconductor storage device comprises the steps of:
forming a first insulating film on a semiconductor substrate;
forming a conductive film on the first insulating film;
forming a protective film on the conductive film;
etching the protective film and conductive film locally and forming first and second wirings;
forming a second insulating film between the first and second wirings;
etching the second insulating film and first insulating film locally by using the protective film as a mask and forming a contact hole between the first and second wirings; and
forming a third insulating film at least on a side wall of the conductive film and on a side wall of the first insulating film in the contact hole.
REFERENCES:
patent: 4977105 (1990-12-01), Okamoto et al.
patent: 5037777 (1991-08-01), Mele et al.
patent: 5055423 (1991-10-01), Smith et al.
patent: 5061650 (1991-10-01), Dennison et al.
patent: 5082797 (1992-01-01), Chan et al.
patent: 5200358 (1993-04-01), Bollinger et al.
patent: 5275972 (1994-01-01), Ogawa et al.
patent: 5279982 (1994-01-01), Crotti
patent: 5312769 (1994-05-01), Matsuo et al.
patent: 5466639 (1995-11-01), Ireland
patent: 5482894 (1996-01-01), Havemann
patent: 5578524 (1996-11-01), Fukase et al.
patent: 5631179 (1997-05-01), Sung et al.
patent: 5643833 (1997-07-01), Tsukamoto
patent: 5667918 (1997-09-01), Brainerd et al.
patent: 5828094 (1998-10-01), Lee
patent: 5840621 (1998-11-01), Kasai
patent: 5841195 (1998-11-01), Lin et al.
patent: 2249429 (1992-05-01), None
Kohyama Yusuke
Ohsawa Takashi
Sawada Shizuo
Banner & Witcoff , Ltd.
Kabushiki Kaisha Toshiba
Malsawma Lex H.
Smith Matthew
LandOfFree
Stacked capacitor-type semiconductor storage device and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stacked capacitor-type semiconductor storage device and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stacked capacitor-type semiconductor storage device and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3105981