Stacked capacitor dram cell and method of fabricating

Details Stacked capacitor dram cell and method of fabricating Stacked capacitor dram cell and method of fabricating

1991-12-20

1992-06-30

Griffin, Donald

Electricity: electrical systems and devices

Electrostatic capacitors

Fixed capacitor

357 236, 437 48, H01G 406, H01L 2170, H02L 2978

Patent

active

051269163

ABSTRACT:
A DRAM having stacked high capacitance capacitors formed by depositing a thick undoped polysilicon layer over field oxide areas thereon, patterning the polysilicon layer so as to have portions over the planned stacked capacitor areas, forming a silicon oxide layer on the exposed surface of the polysilicon, removing the silicon oxide layer from horizontal surfaces of the polysilicon layer by anisotropic etching, removing the polysilicon layer by isotropic etching leaving vertical silicon oxide structures, and forming openings to desired source/drain structures of the DRAM using lithography and etching. A bottom electrode polysilicon layer is deposited over the device and field oxide areas to make contact to the source/drain structures. A capacitor dielectric layer is formed over the bottom electrode polysilicon layer. A contact polysilicon layer is deposited as the top storage node electrode and the contact polysilicon layer and the dielectric layers are patterned.

REFERENCES:
patent: 4700457 (1987-10-01), Matsukawa
patent: 4742018 (1988-05-01), Kimura et al.
patent: 4910566 (1990-03-01), Ema
patent: 4914546 (1990-04-01), Alter
patent: 4951175 (1990-08-01), Kurosawa et al.
patent: 5028990 (1991-07-01), Kotaki et al.
patent: 5047817 (1991-09-01), Wakamiya et al.
IEEE Spectrum Nov. 1990 Fujio Masuoka pp. 109-112.
IEDM 1988 T. Ema et al. pp. 592-595.

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