Stacked bit-line architecture for high density cross-point memor

Details Stacked bit-line architecture for high density cross-point memor Stacked bit-line architecture for high density cross-point memor

1990-04-20

1992-04-21

Popek, Joseph A.

Static information storage and retrieval

Interconnection arrangements

365 72, 365149, G11C 506, G11C 1124

Patent

active

051074591

ABSTRACT:
A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

REFERENCES:
patent: 4156938 (1979-05-01), Proebsting et al.
patent: 4402063 (1983-08-01), Wittwer
patent: 4476547 (1984-10-01), Miyasaka
patent: 4570241 (1986-02-01), Arzubi
patent: 4710789 (1987-12-01), Furutani et al.
patent: 4816884 (1989-03-01), Hwang et al.
patent: 4922453 (1990-05-01), Hidaka
Mashiko, K. et al., "A 90ns 4Mb Dram in a 300 mil DIP", ISSCC Digest of Technical Papers, 12 (1987) (Mashiko I).
Mashiko, K. et al., "A 4-Mbit DRAM with Folded-Bit-Line Adaptive Sidewall-Isolated Capacitor (FASIC) Cell", IEEE J. Solid-State Circuits, 22 (5):643 (1987) (Mashiko II).
Shah, A. H. et al., "A 4-Mbit DRAM with Trench-Transistor Cell" IEEE J. Solid State Circuits, 21 (5):618 (1986) (Shah I).
Shah, A. H., et al. "A 4Mb DRAM with Cross-Point Trench Transistor Cell", ISSCC Digest of Technical Papers, 268 (1986) (Shah II).
Hwang, W. et al., "Folded Bit Line Configuration" IBM Technical Disclosure Bulletin, 30 (3):1314 (1987).
Dhong, S. H. et al., "Double-Traversing Pseudo-Folded-Bitlin Design for Cross-Point Memory Cells", IBM Technical Disclosure Bulletin, 30 (11):246 (1988).
Arzubi, L. et al., "One-Device Memory Cell Arrangement with Improved Sense Signals", IBM Technical Disclosure Bulletin, 23 (6):2331 (1980).
Arzubi, L., "Folded Bit Line Connection to Sense Latch", IBM Technical Disclosure Bulletin, 24 (9):4800 (1982).
Nagatomo, M. et al, "A High Density 4M DRAM Process Using Folded Bit Line Adaptive Side-Wall Isolated Capacitor (FASIC) Cell" IEDM Technical Digest, 144 (1986).

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