Stacked alignment mark and method for manufacturing thereof

Details Stacked alignment mark and method for manufacturing thereof Stacked alignment mark and method for manufacturing thereof

2007-10-30

2007-10-30

Potter, Roy (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S797000

Reexamination Certificate

active

11162117

ABSTRACT:
A stacked alignment mark. The stacked alignment mark comprises a first alignment mark and a second alignment mark. The first alignment mark is located in a first film layer, wherein the first alignment mark is composed of a plurality of conductive wires. The second alignment mark is located in a second film layer under the first film layer. The first alignment mark is located in a first region corresponding to a second region in which the second alignment mark is located. Moreover, the second alignment mark at least contains a third region directly under a space between each two adjacent first conductive wires.

REFERENCES:
patent: 6420791 (2002-07-01), Huang et al.

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