Stackable vertical thin package/plastic molded lead-on-chip memo

Details Stackable vertical thin package/plastic molded lead-on-chip memo Stackable vertical thin package/plastic molded lead-on-chip memo

1993-09-03

1995-10-10

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437209, 437214, 437215, 437220, H01L 2160

Patent

active

054570719

ABSTRACT:
This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal heat sink arranged with respect to the remainder of the package to balance the stresses induced in the package during fabrication. This is accomplished by placing a lead frame on the active face of the semiconductor chip, bonding the lead frame conductors to respective input/output pads on the active face of the chip, and molding an encapsulant completely around five of the six sides of the chip but leaving a substantial portion of the sixth side unencapsulated. A heat sink is affixed on the exposed, i.e. unencapsulated, portion of the sixth side of the chip. The heat sink is comprised of a metal capable of thermally conducting and dissipating waste heat away from the chip and is of a mass, thickness, and area to counterbalance stresses such, as bending stresses, introduced into the chip by the application of the lead frame and encapsulant to the chip. The heat sink can also employed as a ground plane to provide an electromagnetic shield when the chips are arranged in a stack.

REFERENCES:
patent: 3922712 (1975-11-01), Stryker
patent: 4862245 (1989-08-01), Pashby et al.
patent: 5134094 (1992-07-01), Schovanec
patent: 5198888 (1993-03-01), Sugano et al.
patent: 5275975 (1994-01-01), Baudouin et al.
patent: 5286679 (1994-02-01), Farnworth

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