Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Insulating material
Patent
1994-09-22
1996-08-06
Crane, Sara W.
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Insulating material
257666, 257787, H01L 2310, H01L 2334
Patent
active
055436609
ABSTRACT:
This is a semiconductor chip package configuration particularly suited for stacking. These described arrangement is especially adapted to be used with the so-called Lead-On-Chip type package. Each package is of minimum size, and provided with a thermal heat sink arranged with respect to the remainder of the package to balance the stresses induced in the package during fabrication. This is accomplished by placing a lead frame on the active face of the semiconductor chip, bonding the lead frame conductors to respective input/output pads on the active face of the chip, and molding an encapsulant completely around five of the six sides of the chip but leaving a substantial portion of the sixth side unencapsulated. A heat sink is affixed on the exposed, i.e. unencapsulated, portion of the sixth side of the chip. The heat sink is comprised of a metal capable of thermally conducting and dissipating waste heat away from the chip and is of a mass, thickness, and area to counterbalance stresses such, as bending stresses, introduced into the chip by the application of the lead frame and encapsulant to the chip. The heat sink can also employed as a ground plane to provide an electromagnetic shield when the chips are arranged in a stack.
REFERENCES:
patent: 4209798 (1980-06-01), Berreta
patent: 4894706 (1990-01-01), Sato et al.
patent: 5266834 (1993-11-01), Nishi et al.
patent: 5424580 (1995-06-01), Tustaniwskyj et al.
patent: 5444602 (1995-08-01), Banerjee et al.
Clark S. V.
Crane Sara W.
International Business Machines Corp.
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