Stackable test apparatus for protecting integrated circuit...

Details Stackable test apparatus for protecting integrated circuit... Stackable test apparatus for protecting integrated circuit...

2005-09-27

2005-09-27

Lebentritt, Michael (Department: 2812)

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

Multiple housings

C257S777000

Reexamination Certificate

active

06949817

ABSTRACT:
A stackable test apparatus is disclosed including a body having a first surface with a raised portion extending from the first surface along a perimeter of the body and a plurality of stacking pins extending away from the first surface arraigned in a stacking pin pattern. Also included is a plurality of stacking pin receivers located on a second surface of the body, the stacking pin receivers arraigned in a pattern to match the stacking pin pattern and sized to accept the stacking pin.

REFERENCES:
patent: 3999105 (1976-12-01), Archey et al.
patent: 4174424 (1979-11-01), Jurva et al.
patent: 5255795 (1993-10-01), Kitmitto
patent: 6577013 (2003-06-01), Glenn et al.
MIL-STD-883E, Method 1014.10, Mar. 14, 1995, downloaded from the Internet, 12 pgs.

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