Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings
Reexamination Certificate
2000-05-08
2002-07-23
Cao, Phat X. (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
Multiple housings
C257S712000, C257S777000, C257S723000, C257S676000
Reexamination Certificate
active
06424031
ABSTRACT:
BACKGROUND OF THE INVENTION
It is known to include a plurality of integrated circuits in a single package body as a way to increase the density of integrated circuits on a printed circuit board. U.S. Pat. No. 5,815,372 provides examples of packages having two integrated circuits.
Another method to increase package density is to mount a first small outline integrated circuit package (“SOIC”) having either gull wing or J lead styles on a printed circuit board. Next, the leads of a second SOIC package are cut so as to form lead stubs. The second SOIC package is then stacked on the first SOIC package, and the lead stubs are soldered to the leads of the first SOIC package. Unfortunately, this method is difficult and time consuming. Moreover, the footprint of the first SOIC package is relatively large due to the gull wing or J-style leads.
U.S. Pat. No. 5,835,988 discloses packages that can be stacked in multiple layers. It appears that the packages of
FIG. 12
of the patent would be difficult to stack, because no provision is made to align the packages vertically. The embodiment of
FIG. 13
of the patent employs an external leadframe between the packages, but the number of packages that can be stacked is preordained by the size of the leadframe.
SUMMARY OF THE INVENTION
The present invention provides a stackable package for an electronic device, such as an integrated circuit (e.g., a flip chip or a wire bonded integrated circuit.) The packages can be easily stacked one on top of the other. Keys and keyholes of the packages allow the packages to be stacked so that the leads of one package correctly superimpose mirror image leads of the other package, thereby allowing reliable electrical interconnections between the packages. In addition, the present invention provides a heat sink that can be inserted between the stacked packages to radiate heat.
One embodiment of a package within the present invention includes a flip chip integrated circuit encapsulated within a package body. A surface of the flip chip is exposed at a first side of the package body. Leads extend from the package body. A first portion of each lead is embedded in the package body. A surface of the embedded first portion of the lead is exposed at an opposite second side of the package body. A second portion of each lead extends vertically along the package sides, and a third portion extends over the first side of the package body. The third portion of the leads may be located within a recess formed in the first side of the package body, thereby allowing a thinner package. Keys extend from either the first or second sides of the package body, and keyholes are formed in the other of the first or second sides of the package body. The keys facilitate precise stacking of one package on another package. The keys of one package engage the keyholes of the other package stacked therewith.
In another embodiment of the present invention, a pair of such packages are stacked one on top of the other. A planar metal heat sink is disposed between the two packages. The heat sink includes a rectangular body and fins that radiate outward from each edge of the rectangular body. The fins are narrower than the space between adjacent leads of the packages. The body of the heat sink includes pairs of projections and recesses. The projections of the heat sink engage the keyholes of one of the stacked packages, and the recesses of the heat sink are filled by keys of the other package. The body of the heat sink is in contact with the exposed second surface of the flip chip of at least one of the packages, and thereby conducts heat from the flip chip. Absorbed heat is radiated by the fins.
In an alternative embodiment, the packages may include an integrated circuit mounted on a die pad. A surface of the die pad is exposed at the second side of the package body. Two such packages may be stacked with a heat sink between the packages. The heat sink contacts the exposed die pad of the upper package and thereby absorbs heat generated by the integrated circuit.
These and other features and advantages of the present invention will be further apparent in view of the drawings and exemplary embodiments described below.
REFERENCES:
patent: 3838984 (1974-10-01), Crane et al.
patent: 4159221 (1979-06-01), Schuessler
patent: 4398235 (1983-08-01), Lutz et al.
patent: 4833568 (1989-05-01), Berhold
patent: 4996587 (1991-02-01), Hinrichsmeyer et al.
patent: 5068713 (1991-11-01), Toda
patent: 5230759 (1993-07-01), Hiraiwa
patent: 5239198 (1993-08-01), Lin
patent: 5258094 (1993-11-01), Furui et al.
patent: 5266834 (1993-11-01), Nishi et al.
patent: 5270488 (1993-12-01), Ono et al.
patent: 5332864 (1994-07-01), Liang et al.
patent: 5381047 (1995-01-01), Kanno
patent: 5394010 (1995-02-01), Tazawa et al.
patent: 5414300 (1995-05-01), Tozawa et al.
patent: 5435057 (1995-07-01), Bindra et al.
patent: 5455387 (1995-10-01), Hoffman et al.
patent: 5521429 (1996-05-01), Aono et al.
patent: 5587341 (1996-12-01), Masayuki et al.
patent: 5594275 (1997-01-01), Kwon et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 5656856 (1997-08-01), Kweon
patent: 5677569 (1997-10-01), Choi et al.
patent: 5715147 (1998-02-01), Nagano
patent: 5742007 (1998-04-01), Kornowski et al.
patent: 5744827 (1998-04-01), Jeong
patent: 5760471 (1998-06-01), Fujisawa et al.
patent: 5801439 (1998-09-01), Fujisawa
patent: 5835988 (1998-11-01), Ishii
patent: 5859471 (1999-01-01), Kuraishi et al.
patent: 5877043 (1999-03-01), Alcoe et al.
patent: 5880403 (1999-03-01), Czajkowski et al.
patent: 5883426 (1999-03-01), Tokuno
patent: 5950074 (1999-09-01), Glenn et al.
patent: 5962810 (1999-10-01), Glenn
patent: 5977613 (1999-11-01), Takata et al.
patent: 5986209 (1999-11-01), Tandy
patent: 5994166 (1999-11-01), Akram
patent: 6043430 (2000-03-01), Chun
patent: 6091142 (2000-07-01), Lee
patent: 6114221 (2000-09-01), Tonti et al.
patent: 6130115 (2000-10-01), Okumura et al.
patent: 6143981 (2000-11-01), Glenn
patent: 6197615 (2001-03-01), Song et al.
patent: 6225146 (2001-05-01), Yamaguchi et al.
patent: 6242281 (2001-06-01), Mclellan et al.
patent: 6271059 (2001-08-01), Bertin et al.
patent: 6281568 (2001-08-01), Glenn et al.
patent: 0 794 572 (1997-09-01), None
patent: 60-236756 (1985-10-01), None
patent: 1-106456 (1989-04-01), None
patent: 2-239651 (1990-09-01), None
patent: 03-163583 (1991-06-01), None
patent: 406151656 (1994-05-01), None
patent: 9-8205 (1997-01-01), None
Amkor Technology Inc.
Cao Phat X.
Le Thao X.
Parsons James E.
Skjerven Morrill LLP
LandOfFree
Stackable package with heat sink does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stackable package with heat sink, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stackable package with heat sink will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2873739