Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – With large area flexible electrodes in press contact with...
Reexamination Certificate
2000-05-19
2002-02-26
Pham, Long (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
With large area flexible electrodes in press contact with...
C257S698000
Reexamination Certificate
active
06351029
ABSTRACT:
STATEMENT RE: FEDERALLY SPONSORED RESEARCH/DEVELOPMENT
(Not Applicable)
BACKGROUND OF THE INVENTION
The present invention relates generally to chip stacks, and more particularly to a stackable integrated circuit chip package including a flex circuit which allows multiple chip packages to be quickly, easily and inexpensively assembled into a chip stack having a minimal profile.
Multiple techniques are currently employed in the prior art to increase memory capacity on a printed circuit board. Such techniques include the use of larger memory chips, if available, and increasing the size of the circuit board for purposes of allowing the same to accommodate more memory devices or chips. In another technique, vertical plug-in boards are used to increase the height of the circuit board to allow the same to accommodate additional memory devices or chips.
Perhaps one of the most commonly used techniques to increase memory capacity is the stacking of memory devices into a vertical chip stack, sometimes referred to as 3D packaging or Z-Stacking. In the Z-Stacking process, from two (2) to as many as eight (8) memory devices or other integrated circuit (IC) chips are interconnected in a single component (i.e., chip stack) which is mountable to the “footprint” typically used for a single package device such as a packaged chip. The Z-Stacking process has been found to be volumetrically efficient, with packaged chips in TSOP (thin small outline package) or LCC (leadless chip carrier) form generally being considered to be the easiest to use in relation thereto. Though bare dies or chips may also be used in the Z-Stacking process, such use tends to make the stacking process more complex and not well suited to automation.
In the Z-Stacking process, the IC chips or packaged chips must, in addition to being formed into a stack, be electrically interconnected to each other in a desired manner. There is known in the prior art various different arrangements and techniques for electrically interconnecting the IC chips or packaged chips within a stack. Examples of such arrangements and techniques are disclosed in Applicant's U.S. Pat. No. 4,956,694 entitled INTEGRATED CIRCUIT CHIP STACKING issued Sep. 11, 1990, U.S. Pat. No. 5,612,570 entitled CHIP STACK AND METHOD OF MAKING SAME issued Mar. 18, 1997, and U.S. Pat. No. 5,869,353 entitled MODULAR PANEL STACKING PROCESS issued Feb. 9, 1999.
The various arrangements and techniques described in these issued patents and other currently pending patent applications of Applicant have been found to provide chip stacks which are relatively easy and inexpensive to manufacture, and are well suited for use in a multitude of differing applications. The present invention provides yet a further alternative arrangement and technique for forming a chip stack which involves the use of stackable integrated circuit chip packages including flex circuits. The inclusion of the flex circuits in the chip packages of the present invention provides numerous advantages in the assembly of the chip stack, including significant increases in the production rate and resultant reductions in cost attributable to the reduced complexity of the assembly process.
SUMMARY OF THE INVENTION
In accordance with a first embodiment of the present invention, there is provided a stackable integrated circuit chip package which comprises a flex circuit. The flex circuit itself comprises a flexible substrate having opposed, generally planar top and bottom surfaces. Disposed on the flex circuit is a conductive pattern. In addition to the flex circuit, the chip package comprises a frame which is attached to the substrate of the flex circuit. Also included in the chip package is an integrated circuit chip which is at least partially circumvented by the frame and electrically connected to the conductive pattern. The substrate is wrapped about and attached to at least a portion of the frame such that the conductive pattern defines first and second portions which are each electrically connectable to another stackable integrated circuit ship package.
In the first embodiment, the frame preferably has a generally rectangular configuration defining opposed pairs of longitudinal and lateral sides. The frame also defines a central opening for receiving the integrated circuit chip, with the top and bottom surfaces of the frame being attached to the top surface of the substrate. The substrate is preferably wrapped about the frame such that the first portion of the conductive pattern extends over a portion of the bottom surface of the frame, with the second portion of the conductive pattern extending over a portion of the top surface of the frame. More particularly, the substrate is wrapped about the longitudinal sides of the frame such that the first and second portions of the conductive pattern extend in spaced, generally parallel relation to each other over respective portions of the bottom and top surfaces of the frame.
The substrate itself preferably has a generally rectangular configuration defining a pair of longitudinal peripheral edge segments and a pair of lateral peripheral edge segments. The conductive pattern extends along the bottom surface of the substrate to the longitudinal peripheral edge segments thereof, with the substrate preferably being wrapped about the longitudinal sides of the frame such that the longitudinal peripheral edge segments of the substrate extend along respective ones of the longitudinal sides of the frame. The substrate is also sized relative to the frame such that the lateral sides of the frame protrude from respective ones of the lateral peripheral edge segments of the substrate, with the longitudinal peripheral edge segments of the substrate also extending to the central opening of the frame. In the chip package of the first embodiment, a pair of heat sinks may be attached to one or both of the lateral sides of the frame which extend beyond the lateral peripheral edge segments of the substrate.
The conductive pattern of the chip package of the first embodiment preferably comprises a first set of pads which are disposed on the bottom surface of the substrate, and a second set of pads which are disposed on the top surface of the substrate and electrically connected to respective ones of the pads of the first set. The integrated circuit chip is itself electrically connected to the pads of the second set. A plurality of copper bumps or solder bumps may be formed on respective ones of the pads of the first set for facilitating the electrical connection of the chip package to a mother board. The pads of the second set are preferably arranged in an identical pattern to those of the first set such that the pads of the second set are aligned with and electrically connected to respective ones of the pads of the first set. The electrical connection of the pads of the first and second sets to each other is preferably accomplished through the use of vias which are formed in the substrate and extend between respective aligned pairs of the pads of the first and second sets.
The integrated circuit chip of the chip package of the first embodiment preferably comprises a body having opposed, generally planar top and bottom surfaces. In addition to the body, the integrated circuit chip includes a plurality of conductive contacts which are disposed on the bottom surface of the body. The conductive contacts of the integrated circuit chip are electrically connected to respective ones of the pads of the second set. The conductive contacts are preferably arranged on the bottom surface of the body in an identical pattern to the pads of the second set, and are preferably electrically connected to respective ones of the pads of the second set via solder. The integrated circuit chip is preferably selected from the group consisting of a flip chip device and a fine pitch BGA device.
In the chip package of the first embodiment, a layer of epoxy is preferably disposed between the bottom surface of the body and the top surface of the substrate. Additionally, the substrate is preferably attached to the fram
Pham Long
Pham Thanh V
Stetina Brunda Garred & Brucker
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