Stackable chip scale semiconductor package with mating contacts

Details Stackable chip scale semiconductor package with mating contacts Stackable chip scale semiconductor package with mating contacts

1998-04-01

2000-01-11

Williams, Alexander Oscar

Active solid-state devices (e.g., transistors, solid-state diode

Housing or package

With contact or lead

257737, 257738, 257680, 257686, 257774, 257777, 257723, H01L 2350, H01L 2312, H01L 2336, H05K 118

Patent

active

06013948&

ABSTRACT:
A stackable chip scale semiconductor package and a method for fabricating the package are provided. The package includes a substrate having a die mounting site wherein a semiconductor die is mounted. The package also includes first contacts formed on a first surface of the substrate, and second contacts formed on an opposing second surface of the substrate. Conductive vias in the substrate electrically connect the first contacts to the second contacts. In addition, the first contacts and the second contacts have a mating configuration, such that a second package can be stacked on and electrically connected to the package. The method for fabricating the package includes the steps of: laser machining and etching the vias, forming an insulating layer in the vias, and then depositing a conductive material within the vias.

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"Chip Scale Review", vol. 1, No. 1, May 1997.

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