Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package
Reexamination Certificate
2001-08-06
2002-06-18
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Housing or package
C257S678000, C257S685000, C257S686000, C438S106000, C438S109000, C438S121000, C438S123000, C438S127000
Reexamination Certificate
active
06407448
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a stackable ball grid array (BGA) semiconductor package and a fabrication method thereof.
2. Background of the Related Art
Currently, there is an effort to produce a highly integrated semiconductor package having a large number of exterior connections. One example is a BGA semiconductor package in which a plurality of solder balls which are attached to a substrate are used as external terminals. In these BGA packages, a plurality of solder balls are attached to an upper or a lower surface of a substrate by the application of heat. The solder balls, which act as external terminals, are not easily bent or deformed by inpacts with solid objects.
FIG. 1
shows a structure of a background art BGA semiconductor package. As seen in
FIG. 1
, an elastomer
2
is attached to a center portion of an upper surface of a semiconductor chip
1
, and a high strength adhesive resin
3
is formed on the elastomer
2
. A plurality of metal traces, which transmit electric signals, are formed on the adhesive resin
3
. First ends
4
a
of the metal traces extend across a top surface of the adhesive resin
3
, and second ends
4
b
of each of the metal traces are connected to chip pads
6
formed on a marginal portion of the upper surface of the semiconductor chip
1
. A solder resist
5
covers the metal traces
4
a
and the adhesive resin
3
, except for exposed portions of the first ends
4
a
of the metal traces, onto which solder balls will be attached. An encapsulant
7
, such as a molding resin, covers the upper surface of the semiconductor chip
1
, and the portions of the metal traces that are not covered with the solder resist
5
. Conductive balls
8
are then attached to the exposed portions of the metal traces to serve as output terminals.
Since the conductive balls are exposed on only one side of the package (in
FIG. 1
, the conductive balls are exposed at the upper surface thereof), it is impossible to fabricate a stackable package of high mount density.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a stackable BGA semiconductor package, and a fabrication method thereof, that maintain advantages of the conventional BGA package.
A stackable chip package embodying the invention includes a supporting member having a plurality of conductive patterns formed therein. A plurality of first conductive traces are formed on a surface of the supporting member, and respective ones of the first conductive traces are coupled to corresponding ones of the conductive patterns. A chip having chip pads is attached to a second surface of the supporting member, and a plurality of second conductive traces are arranged over the chip. Respective ones of the second conductive traces are electrically coupled to corresponding chip pads on the chip, and corresponding ones of the conductive patterns in the supporting member. An embodiment of the invention could also include a solder resist that covers selected portions of the first and second conductive traces. The solder resist would leave connecting portions of the first and second conductive traces exposed. Exterior leads, in the form of conductive balls, could then be connected to the connecting portions of the first and second conductive traces. A device embodying the invention could also include a molding resin that encapsulates portions of the conductive traces and the chip. The supporting member could include a supporting plate and a supporting frame that surrounds the supporting plate.
In a method embodying the invention, a supporting member having a plurality of conductive patterns is first formed. A plurality of first conductive traces are then formed on a first surface of the supporting member such that the conductive traces are electrically coupled to corresponding ones of the conductive patterns in the supporting member. A plurality of second traces are then attached to a surface of a chip, and the chip is attached to a second surface of the supporting member. Respective ones of the second conductive traces are attached to corresponding chip pads on the chip, and to corresponding ones of the conductive patterns in the supporting member. A method embodying the invention could also include the step of forming layers of solder resist over the first and second conductive traces, and removing portions of the solder resist to expose connecting portions of the first and second conductive traces. A method embodying the invention could also include attaching leads, in the form of conductive balls, to respective ones of the exposed connecting portions of the first and second conductive traces.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
REFERENCES:
patent: 5045921 (1991-09-01), Lin et al.
patent: 5477611 (1995-12-01), Sweis et al.
patent: 5625221 (1997-04-01), Kim et al.
patent: 5776796 (1998-07-01), Distefano et al.
patent: 5783870 (1998-07-01), Mostafazazdeh et al.
patent: 5793118 (1998-08-01), Nakajima
patent: 5930598 (1999-07-01), Wille et al.
patent: 5933709 (1999-08-01), Chun
patent: 5950072 (1999-09-01), Queyssac
patent: 5977640 (1999-11-01), Bertin et al.
patent: 5994166 (1999-11-01), Akram et al.
patent: 6020633 (2000-02-01), Erickson
patent: 6020637 (2000-02-01), Karnezor
patent: 6025258 (2000-02-01), Ochiai et al.
patent: 6028365 (2000-02-01), Akram et al.
patent: 6051890 (2000-04-01), Mozdzen
patent: 6054337 (2000-04-01), Solberg
patent: 6072233 (2000-06-01), Corisis et al.
patent: 6093584 (2000-07-01), Fjelstad
patent: 6117705 (2000-09-01), Glenn et al.
patent: 6172423 (2001-01-01), Lee
patent: 6180881 (2001-01-01), Isaak
patent: 6313522 (2001-11-01), Akram et al.
Fleshner & Kim LLP
Hyundai Electronics Industries Co., Inc.
Lee Jr. Granvill D
LandOfFree
Stackable ball grid array semiconductor package and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Stackable ball grid array semiconductor package and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Stackable ball grid array semiconductor package and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2960519