Stack structure of semiconductor packages and method for...

Active solid-state devices (e.g. – transistors – solid-state diode – Housing or package – Multiple housings

Reexamination Certificate

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C257S690000, C257S738000, C257S779000, C257S780000, C257SE23003, C257SE23020

Reexamination Certificate

active

07855443

ABSTRACT:
A stack structure of semiconductor packages and a method for fabricating the stack structure are provided. A plurality of electrical connection pads and dummy pads are formed on a surface of a substrate of an upper semiconductor package and at positions corresponding to those around an encapsulant of a lower semiconductor package. Solder balls are implanted to the electrical connection pads and the dummy pads. The upper semiconductor package is mounted on the lower semiconductor package. The upper semiconductor package is electrically connected to the lower semiconductor package by the solder balls implanted to the electrical connection pads, and the encapsulant of the lower semiconductor package is surrounded and confined by the solder balls implanted to the dummy pads. Thereby, the upper semiconductor package is properly and securely positioned on the lower semiconductor package, without the occurrence of misalignment between the upper and lower semiconductor packages.

REFERENCES:
patent: 5222014 (1993-06-01), Lin
patent: 6987314 (2006-01-01), Yoshida et al.
patent: 2007/0246813 (2007-10-01), Ong et al.
patent: I250627 (2006-03-01), None

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