Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
Reexamination Certificate
2001-01-30
2002-02-05
Kim, Kenneth S. (Department: 2183)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Stack based computer
C711S219000, C712S245000
Reexamination Certificate
active
06345353
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to pointers and, more specifically, to a stack pointer which selects between the next available location in the stack memory and a pre-decremented location in the stack memory and which performs, either a post increment operation or post decrement operation after execution of a current instruction and a method therefor.
2. Description of the Prior Art
A “call” instruction and a “return” instruction are two instructions that work together to allow subroutines to be execute in a processor system. The “call” instruction and the “return” instruction work together to allow the called subroutine to automatically return back to the instruction that called it. This allows for the multiple nesting of subroutines.
During read and write operations to the top of the stack memory, the top of the stack will appear as a set of ordinary Random Access Memory (RAM) locations. In an instruction cycle that has four phases, it is necessary to read the top of the stack memory during the second phase of the instruction cycle and to write to the top of the stack memory during the fourth phase. It is desirable for reads and writes to the top of the stack to operate on the last value written, rather than on a blank location in the stack memory. This requires that the stack pointer be decremented at the very beginning of the second phase so that the last location in the stack memory where data was written may be read.
This creates a timing conflict. A “call” instruction requires that the stack pointer be pointing to the next available location in the stack memory during the second phase of a write operation. However, the stack pointer also needs to be pointing to the directly preceding location during the second phase for a read during a top of stack operation.
Therefore, a need existed to provide an improved stack pointer. The improved stack pointer must be able to pre-decode a decremented value, and to have this value selectable by a multiplexer in order to read this location. The improved stack pointer must further be able to pre-decode a decremented value and to have post increment/decrement options.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the present invention, it is an object of the present invention to provide an improved stack pointer.
It is another object of the present invention to provide an improved stack pointer that is able to pre-decode a decremented value of a stack memory.
It is further object of the present invention to provide an improved stack pointer that is able to pre-decode a decremented value of a stack memory, and to have this value selectable by a multiplexer in order to read the last location in the stack memory where data was written.
It is still another object of the present invention to provide an improved stack pointer that is able to pre-decode a decremented value and to have post increment/decrement options.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
In accordance with one embodiment of the present invention, a pre-decode stack pointer system with post revise operation is disclosed. The stack pointer system has a stack memory device which when used in conjunction with a stack pointer lF stores and retrieves values of a program counter on a first in last out (FILO) basis. The stack pointer is coupled to the stack memory device. The stack pointer is used for generating the next unutilized location in the stack memory device in order to indicate where a current value in the program counter is to be written. The stack pointer also generates a directly preceding location to the next unutilized location in order to read the last value of the program counter that was written to the stack memory device. The stack pointer will select the next unutilized location in the stack memory device for a write operation and the directly preceding location to the next unutilized location in the stack memory device for a read operation. The stack pointer will further perform either a post increment or post decrement operation on the next unutilized location in the stack memory device after execution of a current instruction.
In accordance with another embodiment of the present invention, a method of providing a pre-decode stack pointer system with post revise operation comprising the steps of: providing a stack memory device which stores and retrieves values of a program counter; and providing a stack pointer coupled to the stack memory device for generating the next unutilized location in the stack memory device to indicate where a current value of the program counter is to be written, for generating a directly preceding location to the next unutilized location to read a last value of the program counter written to the stack memory device, for selecting one of the next unutilized location in the stack memory device or the directly preceding location to the next unultilized location in the stack memory device, and for one of post incrementing or post decrementing the next unutilized location in the stack memory device after execution of a current instruction.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawings.
REFERENCES:
patent: 4430711 (1984-02-01), Anderson et al.
patent: 4459659 (1984-07-01), Kim
patent: 4835738 (1989-05-01), Niehaus et al.
patent: 5023828 (1991-06-01), Grundmann et al.
patent: 5193205 (1993-03-01), Matsuo et al.
patent: 5287309 (1994-02-01), Kai
Allen Stephen
Wojewoda Igor
Kim Kenneth S.
Microchip Technology Incorporated
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