Electrical computers and digital processing systems: processing – Architecture based instruction processing – Stack based computer
Reexamination Certificate
1998-08-03
2002-12-31
Maung, Zarni (Department: 2154)
Electrical computers and digital processing systems: processing
Architecture based instruction processing
Stack based computer
C711S132000, C712S210000, C712S032000
Reexamination Certificate
active
06502183
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a data processing device for storing data and executing instructions. Such a data processing device is described in the architectural overview of the Philips 80C51XA processor, published in the 1996 data handbook IC25 published by Philips Semiconductors, pages 33 to 56.
BACKGROUND OF THE INVENTION
A stack can be maintained for example by means of a stack pointer register which stores a memory address pointer. During a push operation the memory address pointer is incremented and information is stored at the memory location to which it points. By means of successive pushes information is thus written into a series of consecutive memory locations. This information can be read by addressing memory locations relative to the top of stack.
The pop operation is the reverse of the push operation. During a pop operation information is read from the memory location to which the address pointer points and the memory address pointer is decremented.
The 80C51XA processor supports such a stack mechanism because it has instructions with an addressing mode in which addresses are expressed by reference to a register which contains a memory address pointer. By referring to a register the instruction identifies memory address pointer in that address as the pointer to the memory location that is to be used as the source of an operand or the destination of a result. Several registers can be used in this way, and therefore each can be used as a stack pointer. The 80C51XA processor also specifically defines a user stack and a system stack for return from procedure calls and interrupts. The stack pointer to these stacks map to one of the normal registers.
There is an addressing mode in which execution an instruction will implicitly cause the register to which it refers to be incremented or decremented together with its functional operation of the instruction. Increments or decrements are in units of 16 bit words addresses, that is, the content of the register is incremented or decremented by 2 byte addresses at a time.
Stacks provide a powerful mechanism for managing information, especially when used to execute programs defined by higher level languages. This means that large numbers of items will be stored on a stack and that a stack will use a considerable amount of randomly accessible memory space.
SUMMARY OF THE INVENTION
Amongst others, it is an object of the invention to provide for a processing device in which less memory space is needed for stacked information.
It is another object of the invention to reduce the amount of memory space needed for storing programs that make use of stacks.
It is another object of the invention to provide a powerful set of stack handling instructions without making instructions unduly large.
The processing device according to the invention is characterized by a means for maintaining push and/or pop information in basic units of a first and second length on a first and second stack respectively, the first and second length being unequal, and not an integer multiple of one another, and where the first stack is used for addressing and the second stack is used for data. The first stack may be used for example for numerical data values, to be used as operands in various arithmetic and/or logic instructions, in which case that basic unit if for example a 16 bit word and the second stack may be used for addresses to be used as addresses for operands in such arithmetic and/or logic instructions, in which case the basic unit is for example a 24 bit word.
Thus, the lengths of basic units are for example 16 bit and 24 bit for the first and second stack respectively. As a result, when a first and second stack pointer are used which point to a memory addressed in terms of bytes, the first stack pointer will be changed by two byte addresses as a result of a push and/or pop and the second stack pointer will be changed by three byte addresses as a result of a push or a pop. The first stack may be used for example for numerical data values, to be used as operands in various arithmetic and/or logic instructions and the second stack may be used for addresses to be used as addresses for operands in such arithmetic and/or logic instructions.
The basic length of data values and addresses will generally differ due to the different use that is made of these two types of information. When, contrary to the invention, only one basic unit length is available for stacking both type s of information this means that storage space on the stack will be wasted on useless information. This is avoided by the invention due to the use of stacks with different lengths for basics tacking units. The invention is not limited to addresses and data: the invention may be used under any circumstances where two types of information with different meaningful lengths are used.
An embodiment of the processing device according to the invention is that the instruction set uses a first and second addressing mode for designating storage locations in terms of an offset relative to a top of the first and second stack respectively, expressability of the offset being restricted to numbers of basic units for one of the first or second stacks. In this embodiment the instructions can be kept short, because they address offsets in units adapted to the relevant stack and no instruction space is wasted by expressing offset which would express finer differences in that stack.
Further embodiments of the processing device according to the invention are that push and pop are coded by sacrificing a small amount of the offsets that can be specified relative to the top of stack, preferably the largest offset.
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IBM Technical Disclosure Bulletin, G.A. Gates et al., “Multiword Size Storage”, vol. 11, No. 8, Jan. 1969, pp. 1019-1020.*
“XA User Guide”, pp. 33-57, Jul. 21, 1995. (supplied by applicant with the application filed on Aug. 3, 1998).*
* Copy of the reference is not being furnished because it was an Applicant supplied document.*
Philips Semiconductor Data Book, IC25, 1996; pp. 33-56.
Lippens Paul E. R.
Vlot Marnix C.
Koninklijke Philips Electronics , N.V.
Lin Wen-Tai
Maung Zarni
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