Static information storage and retrieval – Interconnection arrangements
Patent
1994-10-20
1996-12-03
Nelms, David C.
Static information storage and retrieval
Interconnection arrangements
365 51, 257686, 257777, 361735, G11C 506, H01L 2302
Patent
active
055814980
ABSTRACT:
An electronic package is disclosed in which a plurality of stacked "same function" IC chips are designed to be used in lieu of a single IC chip, and to fit into a host computer system, in such a way that the system is "unaware" that substitution has been made. Memory packages are of primary interest, but other packages are also feasible, such as packages of FPGA chips. In order to "translate" signals between the host system and the stacked IC chips, it is necessary to include suitable interface circuitry between the host system and the stacked chips. Specific examples are disclosed of a 4 MEG SRAM package containing 4 stacked IC chips each supplying a 1 MEG memory, and of 64 MEG DRAM packages containing 4 stacked IC chips each supplying a 16 MEG memory. The interface circuitry can be provided by a single special purpose IC chip included in the stack, referred to as a VIC chip, which chip provides both buffering and decoding circuitry. Additionally, the VIC chip should provide power supply buffering. And, if it has sufficient real estate, such performance enhancing functions as error correction, memory cache, and synchronized memory may be included in the VIC chip circuitry.
REFERENCES:
patent: 5198888 (1993-03-01), Sugano
patent: 5343075 (1994-08-01), Nishino
patent: 5345412 (1994-09-01), Shiratsuchi
patent: 5347428 (1994-09-01), Carson
Ludwig David E.
Saunders Christ H.
Some Raphael R.
Stuart John J.
Irvine Sensors Corporation
Mai Son
Nelms David C.
Plante Thomas J.
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