Boots – shoes – and leggings
Patent
1987-06-05
1991-10-01
Shaw, Gareth D.
Boots, shoes, and leggings
3642443, 3642627, 364240, 3642477, 3642401, G06F 942, G06F 922, G06F 1340
Patent
active
050539523
ABSTRACT:
A computer is provided as an add-on processor for attachment to a host computer. Included are a single data bus, a 32-bit arithmetic logic unit, a data stack, a return stack, a main program memory, data registers, program memory addressing logic, micro-program memory, and a micro-instruction register. Each machine instruction contains an opcode as well as a next address field and subroutine call/return or unconditional branching information. The return address stack, memory addressing logic, program memory, and microcoded control logic are separated from the data bus to provide simultaneous data operations with program control flow processing and instruction fetching and decoding. Subroutine calls, subroutine returns, and unconditional branches are processed with a zero execution time cost. Program memory may be written as either bytes or full words without read/modify/write operations. The top of data stack ALU register may be exchanged with other registers in two clock cycles instead of the normal three cycles. MVP-FORTH is used for programming a microcode assembler, a cross-compiler, a set of diagnostic programs, and microcode.
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Haydon Glen B.
Koopman, Jr. Philip J.
Anderson Edward B.
Kulik P. V.
Shaw Gareth D.
WISC Technologies, Inc.
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