Stack frame cache on a microprocessor chip

Details Stack frame cache on a microprocessor chip Stack frame cache on a microprocessor chip

1986-05-16

1989-03-07

Zache, Raulfe B.

Boots, shoes, and leggings

G06F 1208

Patent

active

048112089

ABSTRACT:
A plurality of global registers are provided on the microprocessor chip. One of a global registers is a frame pointer register containing the current frame pointer, and the remainder of the global registers are available to a current process as general registers. A plurality of floating point registers are also provided for use by the current process in execution of floating point arithmetic operations. A register set pool made up of a plurality of register sets is provided, each register set being comprised of a number of local registers. When a call instruction is decoded, a register set of local registers from the register set pool is allocated to the called procedure, and the frame pointer register is initialized. When a return instruction is decoded, the register set is freed for allocation to another procedure called by a subsequent call instruction. If the register set pool is depleted a register set associated with a previous procedure is saved in the main memory, and that register set is allocated to the current procedure. The local registers in a register set associated with a procedure contain linkage information including a pointer to the previous frame and an instruction pointer, thus enabling most call and return instructions to execute without needing any references to off-chip memory.

REFERENCES:
patent: 4268903 (1981-05-01), Miki et al.
patent: 4445173 (1984-04-01), Pilat et al.
patent: 4516203 (1985-05-01), Farber et al.
patent: 4530049 (1985-07-01), Zee
patent: 4652996 (1987-03-01), Bowden

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