Stack die packages

Details Stack die packages Stack die packages

2009-05-01

2010-11-02

Potter, Roy K (Department: 2822)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Chip mounted on chip

C257S686000, C257S723000, C257S778000

Reexamination Certificate

active

07825521

ABSTRACT:
An integrated circuit package includes a substrate comprising a first contact. A first integrated circuit mechanically attached to the substrate. The first integrated circuit comprising a second contact. A first redistribution layer arranged on the first integrated circuit. The first redistribution layer includes a trace coupled to the second contact. A first wire connects the first contact to the second contact. A flip-chip integrated circuit comprises a third contact connected to the trace by a conductive bump. A second integrated circuit mechanically coupled to the flip-chip integrated circuit. The second integrated circuit comprises a fourth contact. A second wire connects the fourth contact to at least the second contact or the first contact.

REFERENCES:
patent: 5815372 (1998-09-01), Gallas
patent: 6222260 (2001-04-01), Liang
patent: 6271598 (2001-08-01), Vindasius et al.
patent: 2001/0002726 (2001-06-01), Oka et al.
patent: 2003/0122237 (2003-07-01), Saeki
patent: 2005/0212144 (2005-09-01), Rugg et al.
patent: 2006/0094160 (2006-05-01), Akram
patent: 2006/0097284 (2006-05-01), Ronen
patent: 2001 196529 (2001-07-01), None
International Search Report for Application No. PCT/US2007/013821 (corresponding hereto) mailed Jan. 21, 2008; 4 pages.

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