Stack capacitor DRAM cell with buried bit-line and method of man

Details Stack capacitor DRAM cell with buried bit-line and method of man Stack capacitor DRAM cell with buried bit-line and method of man

1993-08-26

1994-11-29

Thomas, Tom

Fishing, trapping, and vermin destroying

437 48, 437 60, H01L 2170

Patent

active

053690486

ABSTRACT:
A DRAM cell of transistors with a stack capacitor includes a gate comprising a word line formed over the gate oxide layer. The cell is made by depositing a first dielectric layer over the gate, etching through the first dielectric layer to form a bit-line contact opening therein exposing a portion of the surface of the drain, deposition of a bit-line layer over the product of etching the first dielectric layer and into the bit-line opening, forming a mask and etching the bit-line from the bit-line layer, deposition of second dielectric layer, deposition of a first lower capacitor plate, node contact etching a trench down to expose the source, deposition of dielectric spacer material into the node contact region, masking and etching to form spacers on the side wall of the trench into which node contact is to be made, deposition of a lower capacitor plate layer forming the top portion of a two layer capacitor plate with the first lower capacitor plate layer, the second lower capacitor plate layer extending down into the node contact trench to contact the surface of source, depositing a capacitor dielectric layer over the lower capacitor plate and depositing an upper capacitor plate layer over the capacitor dielectric.

REFERENCES:
patent: 5006481 (1991-04-01), Chan et al.
patent: 5059548 (1991-10-01), Kim
patent: 5061651 (1991-10-01), Imo
patent: 5116776 (1992-05-01), Chan et al.
patent: 5155056 (1992-10-01), Jeong-Gyoo
patent: 5162249 (1992-11-01), Kim
patent: 5166090 (1992-11-01), Kim et al.
"Reliability & Characterization of Composite Oxide/Nitride Dielectrics for Multi-Megabit Dynamic Random Access Memory Stacked Capacitors", J. Electrochem., Soc., vol. 138, No. 7, 2052-2056 (Jul. 1991).
"A New Stacked Capacitor DRAM Cell Characterized by a Storage Capacitor on a Bit-Line Structure" IEDM 596-599 (1988).
"A Capacitor-Over-Bit Line (COB) Cell with a Hemispherical-Grain Storage Node For 64Mb DRAMs" IEDM 90-655 to 90-658 (1990).

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