Stack cache with fixed size stack frames

Details Stack cache with fixed size stack frames Stack cache with fixed size stack frames

1982-02-11

1985-07-16

Heckler, Thomas M.

Boots, shoes, and leggings

G06F 940

Patent

active

045300496

ABSTRACT:
In a programmable system (10) which includes a processor (11) for executing a program structured from a plurality of subprograms, and a stack cache memory (16) for storing subprogram linkage information, the stack (41) is comprised of frames (40) of equal size. Each frame (40) stores the information linking a subprogram to the immediately preceding subprogram. A set of general registers (44) is implemented in each frame (40). Preferably each frame (40) is comprised of a plurality of blocks (42-45) of an equal number of cache memory words (46). The set of general registers (44) occupies one block (44) of the frame (40).
Addressing of individual words (46) in a frame (40) is accomplished via concatenation of a frame pointer (18, 19, 32) a block selector (51, 33), and a word selector (52, 34). Preferably a second memory (12), such as a portion of a main memory, is also included in the system (10) and stores linkage information, such as overflow linkage information. For purposes of communicating with the second memory (12), the cache memory (16) is organized as a buffer.

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