Stable substrate bias generator for MOS circuits

Details Stable substrate bias generator for MOS circuits Stable substrate bias generator for MOS circuits

1987-12-30

1988-12-27

Miller, Stanley D.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307296R, 307351, H03K 1722, H03K 301

Patent

active

047942789

ABSTRACT:
A circuit for controlling substrate bias voltage of a MOS semiconductor substrate. A first level detector monitors the substrate voltage and when the substrate bias falls below a threshold value, the first level detector couples an oscillator to cause a charge pump to pump charges into the substrate until the threshold level is again reached. A second detector operates as an excess negative voltage detector. This second detector monitors the substrate and when the bias voltage exceeds a predetermined limit, the second detector activates a clamper which drives the substrate toward ground potential until the bias voltage is again under the predetermined limit. By this technique the substrate bias is kept between the first threshold level and the maximum limit level. The first and second detectors are comprised of two transistor circuits, wherein the first leg is comprised of a depletion transistor and at least one enhancement transistor coupled between the supply voltage and the substrate. The second leg is comprised of two depletion transistors coupled between the supply voltage and its return. The junction of the depletion and the enhancement transistor of the first leg is coupled to the gate of one of the depletion transistors in the second leg such that the second leg is biased by the voltage on the junction of the transistors of the first leg which monitors the substrate voltage. The two legs determine the activation point of the detectors. The second detector is made to have at least one more enhancement transistor than the first detector to establish the limit level to be above that of the threshold level.

REFERENCES:
patent: 4142114 (1979-02-01), Green
patent: 4356412 (1982-10-01), Moench et al.
patent: 4439692 (1984-03-01), Beekmans et al.
patent: 4454431 (1984-06-01), Hoffmann et al.
patent: 4710647 (1987-12-01), Young
patent: 4752699 (1988-06-01), Cranford, Jr. et al.
"Substrate Voltage Generator with Compensation for Depletion-Mode and Enhancement-Mode Field Effect Transistors", IBM Technical Disclosure Bulletin, vol. 24, No. 7A, Dec. 1981, by G. C. Luckett.
R. A. Blanschild et al., "A New NMOS Temperature-Stable Voltage Reference"; IEEE J. Solid-State Circuits, vol. SC-13; Dec. 1978; pp. 67-73.

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