Stable memory circuit using dual ported VRAM with shift register

Details Stable memory circuit using dual ported VRAM with shift register Stable memory circuit using dual ported VRAM with shift register

1993-09-09

1995-02-28

Dixon, Joseph L.

Boots, shoes, and leggings

364DIG1, 3642463, 364964, 36496431, 36496579, 36523005, 36523003, 395275, G06F 1206, G06F 1216, G06F 1300

Patent

active

053945360

ABSTRACT:
A stable memory circuit which includes a pair of memory banks (2(a)) and (2(b)) each having eight arrays of eight VRAMs (3). Each VRAM (3) is dual-ported and includes a processor port connected to a processor bus (6) and a stable memory port connected to a stable memory bus (7). Accordingly, stable memory operations such as copying operations may be carried out on the stable memory bus (7) concurrently with conventional random accesses by a host processor via the processor port (6) and with very little use of processor time. Further, the stable memory ports of VRAMs (3) are serial ports and each memory bank (2(a)) and (2(b)) may transfer data at high speed using wide serial data path.

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