Stable high speed clock generator

Electrical transmission or interconnection systems – Nonlinear reactor systems – Parametrons

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Details

3072721, 307590, 307595, 307602, 307605, 328 55, 328 63, 328 72, H03K 513, H03K 700, H03K 329

Patent

active

053410319

ABSTRACT:
A clock generator which is provided with a circuit generating non-overlap clock from input clock, a frequency dividing circuit driven by the non-overlap clock and a latch disposed between the frequency dividing circuit and a clock driver, and whose critical pass being a cause of delay is shortened by sampling the frequency-divided output into the latch by the input clock and thereafter driving it by the clock driver, and a clock generator in which an internal clock at high speed in the internal clock logical value generating circuit is added with internal clock edge generating circuit required to operate at high speed and an output of initial stage of a buffer for inputting external clock is divided to supply to the internal clock edge generating circuit and to the other circuits, thereby capacity of the buffer required to operate at high speed in the circuit is decreased to reduce the delay of external clock.

REFERENCES:
patent: 4471299 (1984-09-01), Elmis
patent: 4628269 (1986-12-01), Hunninghaus et al.
patent: 4656649 (1987-04-01), Takahashi
patent: 4700350 (1987-10-01), Douglas et al.
patent: 4758737 (1988-07-01), Hirano
patent: 4761568 (1988-08-01), Stronski
patent: 4816700 (1989-03-01), Imel
patent: 4929854 (1990-05-01), Iino et al.
patent: 4940904 (1990-07-01), Lin
patent: 4975593 (1990-12-01), Kurakazu et al.
patent: 4985640 (1991-01-01), Grochowski et al.
"Non-Overlapping Clock Generator", IBM Technical Disclosure Bulletin, vol. 29, No. 1, Jun. 1986, pp. 263-264.
i82384 Data Book, Intel, Nov. 1986, pp. 4-127.

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