Stable floating gate voltage reference using interconnected...

Miscellaneous active electrical nonlinear devices – circuits – and – Specific identifiable device – circuit – or system – With specific source of supply or bias voltage

Reexamination Certificate

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Reexamination Certificate

active

06768371

ABSTRACT:

BACKGROUND OF THE INVENTION
1. The Field of the Invention
The invention relates generally to analog voltage reference circuits, and more specifically, to programmable voltage reference circuits that use a floating gate to provide a constant charge from which a relatively stable reference voltage may be generated in a manner that is relatively stable over temperature and power supply variations.
2. Background and Related Art
The widespread distribution and advancement of integrated circuits has revolutionized our way of life. Voltage references are typically a key supporting circuit for many fundamental components of analog or mixed-signal integrated circuits. For example, operational amplifiers, voltage comparators, filters, digital-to-analog converter circuits, analog-to-digital converter circuits, all often use voltage references. The voltage reference is typically supplied by a voltage reference circuit. It is often advantageous to the operation of the analog circuit components if the voltage reference circuit is designed to generate a voltage reference that is less dependent on temperature and supply voltage fluctuations.
In the past, many voltage reference circuits have been based on the bandgap voltage of bipolar npn or pnp transistors. Many conventional voltage reference circuits are fabricated using CMOS technology but include parasitic bipolar transistors that are manufactured using custom CMOS processes. The parasitic bipolar transistors are difficult to match and thus have unsupported and inaccurate simulation models as such parasitic bipolar transistors are poorly manufactured and poorly characterized in an otherwise purely CMOS process. Another shortcoming is the difficulty in programming the reference voltage due to needing a post-fabrication programming method, which is usually expensive, time consuming, and/or requires special machinery or external circuitry. Also, many bandgap voltage reference circuits require the matching and cancellation of resistor temperature coefficients, which arc commonly very large and difficult to match.
There have been efforts made to create voltage reference circuits in CMOS processes without using parasitic bipolar devices and without using integrated resistors. Such conventional voltage reference circuits are often not trinmmable and thus compensation for inevitable process deviations is problematic. Furthermore, much of the research in this area is focused on resistor matching on the reference voltage stability.
In the last few decades, floating-gate transistors, which were until then primarily used in digital EEPROM cells, have often been used in analog circuits as a good solution for post-fabrication trimmability. The floating-gate devices are usually MOS transistors with two polysilicon gates, one being fully insulated by oxide layers. Charge can be put on or taken from this insulated gate by Fowler-Nordheim tunneling and/or impact-ionized hot-electron injection as is well known to those of ordinary skill in the art.
Some conventional technology involves the use of floating-gate transistors as a viable alternative to laser trimming, fuse blowing, and digitally controlled resistor trees in a wide variety of analog circuits and building blocks. More recently, voltage reference circuits using one or more floating-gate MOS devices have become common. In conventional technology, the charge on an insulated gate is used to create a voltage, which is then buffered to provide a low temperature coefficient CMOS voltage reference, as shown in FIG.
4
. This architecture resolves the shortcomings of bandgap voltage reference circuits mentioned above. Specifically, it uses no parasitic bipolar transistors, is easily programmable, and uses no integrated resistor. However, the external precision resistors needed for accurate operation make it less useful for fully integrated systems. Also, the insulated gate used in this architecture is very sensitive to capacitive coupling to the drain and source of the transistor, which causes the output voltage to change unnecessarily due to temperature and power supply variations. In one conventional technology, two such floating-gate devices are used where the threshold voltage of each device can be programmed independently, as shown in FIG.
5
. The difference between the two threshold voltages is applied across a diode-connected transistor and is used as the voltage reference output. This architecture also overcomes many of the shortcomings of the bandgap voltage reference circuits and can be fully integrated, but is sensitive to capacitive coupling to other nodes in the circuit. In addition, this architecture requires a voltage reference input of its own.
It would therefore represent an advancement to the art to invent a voltage reference circuit that demonstrates the advantages of floating-gate voltage reference circuits over bandgap voltage reference circuits but overcomes their shortcomings. Especially included in the list of advantageous features are:
1. The property of using only devices that can be easily fabricated and modeled in standard CMOS process, i.e, no parasitic bipolar transistors.
2. The property of being easily programmed across a useful range of reference voltages.
3. The property of not requiring resistors, especially the matching and cancellation of the temperature coefficients of such resistors.
4. The property of being fully integratable.
5. The property of being completely self-contained, i.e, no external voltage references needed.
6. The property of eliminating output voltage variations due to capacitive coupling to the floating gate through temperature and supply voltage fluctuations.
BRIEF SUMMARY OF THE INVENTION
The foregoing problems with the prior state of the art are overcome by the principles of the present invention, which is directed towards a programmable voltage reference circuit that includes a reference voltage output terminal upon which the reference voltage is to be asserted during cooperative interaction of an included current-to-voltage converter circuit, a voltage-to-current converter circuit, and a floating gate.
The current-to-voltage converter circuit has two current input terminals and a voltage output terminal. The voltage-to-current converter circuit has two voltage input terminals and two current output terminals. The two current output terminals are each coupled to a corresponding current input terminal of the current-to-voltage converter circuit. A floating gate device has one terminal coupled to a fixed voltage supply, and one terminal coupled to an input terminal of the voltage-to-current converter. The other input terminal of the voltage-to-current converter is coupled to the voltage reference output terminal of the programmable voltage reference circuit. Also, the voltage output terminal of the current-to-voltage converter circuit is coupled to the negative voltage input terminal of the voltage-to-current converter input circuit. This negative feedback results in the circuit as a whole operating as a unity gain buffer. Such a design enables five of the six advantages enumerated above. The sixth advantage may be obtained by structuring the voltage-to-current and current-to-voltage converter circuit in one of several manners as described further below.
Additional features and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The features and advantages of the invention may be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. These and other features of the present invention will become more fully apparent from the following description and appended claims, or may be learned by the practice of the invention as set forth hereinafter.


REFERENCES:
patent: 5184061 (1993-02-01), Lee et al.
patent: 5629891 (1997-05-01), LeMoncheck et al.
patent: 5898613 (1999-04-01), Diorio et al.
patent: 6133780 (2000-10-01), Chi
patent: 6150872 (2000-11-01), McNeill et a

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