Stable, fast slew, phase locked loop

Details Stable, fast slew, phase locked loop Stable, fast slew, phase locked loop

1980-06-05

1982-07-13

Grimm, Siegfried H.

Oscillators

Automatic frequency stabilization using a phase or frequency...

Afc with logic elements

307516, 307526, 328133, 328134, 331 12, 331 14, 331 27, H03D 1300, H03L 708

Patent

active

043397310

ABSTRACT:
A phase locked loop (10) has a phase insensitive frequency comparator (18) including an up/down counter (26) incremented one way by loop frequency pulses (on 28) and incremented the other way by reference frequency pulses (on 30) and which yields error correction signals (on 22 and 24) to adjust loop frequency when the counter overflows or underflows given limits. Timing means (32) is provided at the input (28, 30) to the counter (26) and prevents any clock pulse from being lost by ensuring a sufficient time gap between pulses. A sample and hold phase detector circuit (16) is provided at the data acquisition input to the loop (10) and enables successful acquisition and lock-on even with many zeros between the incoming data bits, and does so with a minimum number of components.

REFERENCES:
patent: 3825855 (1974-07-01), Basset et al.
patent: 3944940 (1976-03-01), Desai
patent: 3989931 (1976-11-01), Phillips
patent: 4048581 (1977-09-01), Lyberg
patent: 4191976 (1980-03-01), Braun
Messerschmitt, "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery", IEEE Transactions on Communications, vol. COM-27, Sep. 1979, pp. 1288-1295.

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