Stabilizing the lock up of a bi-phase stable FPLL by augmenting

Details Stabilizing the lock up of a bi-phase stable FPLL by augmenting Stabilizing the lock up of a bi-phase stable FPLL by augmenting

1994-12-12

1997-05-06

Kostak, Victor R.

Television

Receiver circuitry

Demodulator

348536, 329360, H04N 5455

Patent

active

056276044

ABSTRACT:
A bi-phase stable FPLL is locked by a DC pilot component in a recovered data signal. The signal is formatted in repetitive data segments including sync characters and a DC pilot. A sign bit, indicative of the polarity of the recovered data, is developed from the sync characters and is used to augment the DC pilot to stabilize the lock up of the FPLL to produce the desired polarity of recovered data.

REFERENCES:
patent: 4091410 (1978-05-01), Citta
patent: 4608604 (1986-08-01), Lilley
patent: 4796102 (1989-01-01), McGinn
patent: 4823399 (1989-04-01), George
patent: 4855835 (1989-08-01), Tobita
patent: 5025455 (1991-06-01), Nguyen
patent: 5087975 (1992-02-01), Citta et al.
patent: 5175626 (1992-12-01), White

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